- Bangalore, Karnataka, India
- On-site
- Full-time · Mid
- 6–8 years
The Engineer will lead Broadcom's design methodology for 5nm and lower technology silicon, focusing on floor-planning, placement, CTS, route, and physical verification.
Responsibilities
- Understanding of SoC for top-down/bottom-up physical design integration in 5nm and lower technologies
- Maintain deep functional knowledge of P&R flows
- Implement timing and functional ECO
- P&R, Extraction, Physical verification, work towards STA closure
- Build automation flows wherever needed/adapt to existing flows for re-use
Requirements
- MSEE
- MSCS
- BSEE
- BSCS