Responsible for the design, the build and the maintenance of the architecture of Equans’s Cyberdefense teams. Propose and test new tools and participate in POCs launched by the cyberdefense teams.
Responsibilities
Design and propose a secure architecture to implement the Cyberdefense tooling and log ingestion capabilities
Adjust collection operations or collection plan to address identified issues/challenges and to synchronize collections with overall operational requirements
Assess and improve the performance of collection assets against prescribed specifications
Identify and mitigate risks to collection management ability to support the plan, operations and target cycle
Monitor operational status and effectiveness of the processing, exploitation and dissemination architecture
Requirements
Engineering degree in cybersecurity
Master’s degree in computer science and networks
proven experience in cybersecurity architecture
Nice to have: Experience in a decentralized and/or international company or organization
Define how engineers and software teams observe and diagnose multi-die computing systems, owning run-control, trace, performance counters, and post-mortem capture from architecture definition through silicon bring-up.
Responsibilities
Own the SoC debug and trace specification, including run-control access, a common trace record format, and observability requirements for bring-up, performance diagnosis, and failure analysis.
Define secure JTAG and run-control behavior for compute engines, cores, management controllers, and other relevant subsystems, including halt and step capabilities.
Specify instruction, compute-engine, microcontroller, fabric-transaction, die-to-die, and network-gateway trace sources.
Architect trace funnels, cross-die triggers, on-chip buffers, and a synchronized package-wide time base aligned with RAS error records.
Define trace capture and export paths, including optional spill to memory and readout over PCIe; set bandwidth limits and measure the effect of tracing on workloads.
Requirements
Bachelor’s degree in Electrical Engineering
Bachelor’s degree in Computer Engineering
Bachelor’s degree in Computer Science
Nice to have: Trace synchronization across multiple dies
As an Hardware Emulation Architect on the HBM architecture team you will be responsible for architecting, enabling, and deploying hardware emulation capabilities for next generation HBM products.
Compensation
The US base salary range that Micron Technology estimates it could pay for this full-time position is: $124,000.00 - $308,000.00 a year
Responsibilities
Develop and maintain hardware emulation environments for complex SoCs and subsystems
Compile, configure, and debug large-scale RTL designs on emulation platforms (e.g., Palladium, Veloce, Zebu)
Support pre-silicon validation, firmware bring-up, and early software development using emulation
Debug functional, performance, and connectivity issues across RTL, firmware, and system layers
Work closely with design, verification, firmware, and architecture teams to enable rapid debug and issue resolution
Requirements
Bachelor’s degree in Electrical Engineering, Computer Engineering, or related field
Master’s degree in Electrical Engineering, Computer Engineering, or related field
As an Hardware Emulation Architect on the HBM architecture team you will be responsible for architecting, enabling, and deploying hardware emulation capabilities for next generation HBM products.
Compensation
The US base salary range that Micron Technology estimates it could pay for this full-time position is: $124,000.00 - $308,000.00 a year
Responsibilities
Develop and maintain hardware emulation environments for complex SoCs and subsystems
Compile, configure, and debug large-scale RTL designs on emulation platforms (e.g., Palladium, Veloce, Zebu)
Support pre-silicon validation, firmware bring-up, and early software development using emulation
Debug functional, performance, and connectivity issues across RTL, firmware, and system layers
Work closely with design, verification, firmware, and architecture teams to enable rapid debug and issue resolution
Requirements
Bachelor’s degree in Electrical Engineering, Computer Engineering, or related field
Master’s degree in Electrical Engineering, Computer Engineering, or related field
Reporting to the Head of Cyber Products, you will be responsible for the design, the build and the maintenance of the architecture of Equans’s Cyberdefense teams. You will be able to propose and test new tools and participate in POCs launched by the cyberdefense teams. You will maintain the collect infrastructure, provide the supervision tools and be responsible for its evolution according to the needs expressed by the SOC. You will be required to test tools in your area.
Responsibilities
Lead with internal teams and external service providers the projects of expansion of the detection perimeter on network, cloud, systems, mobile environments
Propose and follow up the services related to the maintenance in operational and security conditions of the Cyberdefense infrastructure
Manage operationally the service providers
Contribute to the development of infrastructure technical design, manage and participate to integration
Lead and drive system technical designs and roadmaps for Apple’s ecosystem products, overseeing architectural trade‑offs and integrating hardware, software, and mechanical components.
Responsibilities
Work with multi‑discipline teams to design and launch new accessories and features into the market
Decompose user‑facing features, experiences, and functions into associated enabling technologies
Lay out available architectural options, analyze engineering trade‑offs, and articulate recommendations to meet product goals
Work cross‑functionally to understand existing portfolio of technologies, derive capabilities & cost functions, and construct an overall end‑to‑end product solution
Define and author system‑level feature descriptions and detailed functional requirements
Requirements
Bachelor’s Degree in electrical or computer engineering or similar field
Nice to have: Master’s Degree in electrical or computer engineering or similar field
Nice to have: product development experience in a matrix organization
Nice to have: technical lead or engineering manager experience
Nice to have: history of shipping interoperability and ecosystem features
Define resilience across multi-die computing systems, translating reliability targets into hardware, firmware, and software requirements for fault detection, error containment, recovery, and telemetry.
Responsibilities
Own the end-to-end RAS specification, reliability and availability targets, FIT budget by domain, common error records and timestamps, and software-visible error-bank mapping
Define fault detection, correction, logging, and diagnosis across compute engines and cores, caches, HBM and LPDDR memory, die-to-die and scale-up links, PCIe/CXL, and management agents
Specify ECC, parity, residue checks, memory scrubbing, retirement or repair, and in-field screening to prevent and detect silent data corruption
Define end-to-end poison propagation, containment, retry, and recovery for correctable and uncorrectable errors
Specify isolation, fencing, and degraded-operation behavior for compute units, cores or clusters, memory resources, links, and package-level failures
Requirements
Bachelor’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field
Nice to have: Processor error-reporting architectures
Architect responsible for SoC threat modeling, root-of-trust design, secure boot, firmware measurement, and confidential computing across hardware and firmware components.
Responsibilities
Own SoC threat model and security specification
Define root-of-trust architecture and secure boot
Specify device and host attestation
Architect confidential I/O and DMA isolation
Define memory encryption and integrity requirements
Requirements
Bachelor’s degree in Electrical Engineering, Computer Engineering, Computer Science, or related technical field
Lead SoC architecture across multiple teams and disciplines, defining and managing the architecture specification throughout the product life‑cycle.
Locations (2)
Tel Aviv, Tel Aviv, Israel
Haifa, Haifa District, Israel
Responsibilities
Lead SoC architecture across multiple teams and disciplines, including IP architects, design, verification, validation, firmware, security, power management, software and IP development.
Architect and analyze different aspects, including multi chiplets connectivity, chip partitioning, package/board constraints, chip fabric and how SoC subsystems must support them.
Define top-level SoC structures, detailing interconnects, clock distribution, and power domains to ensure seamless system integration and operational efficiency.
Manage the SoC architecture specification and lead it throughout the entire product life‑cycle, concept, modeling, implementation, and silicon bring‑up.
Drive architectural analyses exploring different architectural/implementation alternatives, analyze and recommend the optimal solution balancing between performance, features, power, schedule, and cost.
The salary range is what we believe to be the range of possible compensation for this role at the time of this posting. We may ultimately pay more or less than the posted range and this range is only applicable for jobs to be performed in California, Colorado, New York or remote jobs that can be performed in California, Colorado and New York.
Responsibilities
Design and verify ASIC architectures and digital logic
Build simulations and validate complex hardware designs
Support the ASIC development lifecycle
Optimize performance, power, and reliability
Collaborate across hardware, firmware, and systems engineering teams
Requirements
Bachelor’s, Master’s, or Ph.D. degree in Computer Science, Computer Engineering, Electrical Engineering, Mechanical Engineering, Systems Engineering, Software Engineering, Manufacturing Engineering, Industrial Engineering, Mechatronics, Materials Engineering, Data Science, or a related engineering or technical discipline
Cybersecurity Engineer - Engineering practiceNewEquans France
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