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1–3 jobs· newest first

STA Engineer
Apple · Austin, US+2 more
On-site
Physical Design Engineer
Apple · Texas+4 more
On-site
Physical Design Engineer
Apple · Texas, US+4 more
On-site

+10K new in the last hour

STA Engineer

Apple · Posted Nov 6, 2026

Austin, Texas, United States +2 more
On-site
3+ years

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AI

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Locations (3)

Austin, Texas, United States
Beaverton, Oregon, United States
Cupertino, California, United States

Responsibilities

Lead edge IP development and coordinating with multiple SOC teams
Execute design and integration tasks for high quality IP deliverables
Full chip and block level timing closure ownership throughout the project
Develop and maintain methodology and flows related to timing verification and closure
Generate block and full chip timing constraints

Requirements

Bachelor's Degree

Skills

Digital design fundamentals Scripting languages (TCL and Perl)ASIC design timing concepts STA tools (Primetime)Front end tools and methodologies such as Synthesis, Logic equivalence checks Constraint analysis and debug using Synopsys GCA Timing corners/modes, process variations and signal integrity related issues TCL Perl Primetime Synopsys GCA Synthesis Logic equivalence checks

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Physical Design Engineer

Apple · Posted Nov 5, 2026

Texas, United States +4 more
On-site
10+ years

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Physical Design Engineer

Locations (5)

Texas, United States
California, United States
Beaverton, Oregon, United States
Melbourne, Florida, United States
Waltham, Massachusetts, United States

Responsibilities

Contribute to all phases of physical design of high performance PHY design from RTL to delivery of our final GDSII

Physical Design Engineer

Apple · Posted Nov 5, 2026

Texas, United States +4 more
On-site
10+ years

Apply with RefersoAI Apply on careers page

Physical Design Engineer

Locations (5)

Texas, United States
California, United States
Beaverton, Oregon, United States
Melbourne, Florida, United States
Waltham, Massachusetts, United States

Responsibilities

Contribute to all phases of physical design of high performance PHY design from RTL to delivery of our final GDSII

Requirements

Bachelor's of Science in Electrical Engineering
Nice to have: deep design experience in high PHY and/or SOC designs
Nice to have: knowledge of industry standards and practices in Physical Design
Nice to have: deep understanding of scripting languages
Nice to have: deep understanding of Physical Design Verification methodology

Skills

CAD timing logic design RTL GDSII floor-planning place & route power-grid clock specifications physical verification LVS/DRC HDL Verilog Perl/Tcl extraction STA methodology Power-grid tools STA tools

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Requirements

Bachelor's of Science in Electrical Engineering
Nice to have: High PHY and/or SOC designs
Nice to have: Physical Design standards and practices
Nice to have: Physical Design Verification methodology

Skills

Physical Design PHY design CAD Timing Logic design GDSII Floor-planning Place & Route Power-grid Clock specifications Physical Verification SoC Architecture HDL languages Verilog Power user of industry standard Physical Design & Synthesis tools Perl/Tcl Extraction STA methodology LVS/DRC Perl Tcl STA tools LVS/DRC tools

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