Testbench generation jobs

Understand DFT feature requirements
Implement DFT including Scan, MBIST, TAP, LBIST, IO, SerDes and other I/P DFT integration
Work closely with STA and DI Engineers for test closure
Generate, verify and debug test vectors before tape release
Validate and debug test vectors on ATE during silicon bring up

Requirements

Bachelor's in Electrical/Electronic/Computer Engineering
Master's in Electrical/Electronic/Computer Engineering

Skills

TCL PERL RUBY PYTHON C++DFT background Scan insertion DFT compiler

DFT Engineer

Broadcom · Posted Nov 6, 2026

Open

Austin, Texas, United States
5+ years

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Design, implement, and verify DFT programs for Broadcom ASIC products.

Compensation

The annual base salary range for this position is USD To USD

Responsibilities

Understand DFT feature requirements
Implement DFT including Scan, MBIST, TAP, LBIST, IO, SerDes and other I/P DFT integration
Work closely with STA and DI Engineers for test closure
Generate, verify and debug test vectors before tape release
Validate and debug test vectors on ATE during silicon bring up

Requirements

Bachelor's in Electrical/Electronic/Computer Engineering
Master's in Electrical/Electronic/Computer Engineering

Skills

DFT background Scan insertion and compression ATPG vector generation Verilog coding Testbench generation Memory BIST insertion

Staff DRAM RTL Design Engineer

Micron Technology · Posted Nov 4, 2026

Open

Hyderabad, Telangana, India
6–10 years

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Responsibilities

Take responsibility for designing digital IP blocks from initial microarchitecture to RTL creation, integration, and supporting physical hardware development.
Define and review module interfaces and system-level architecture.
Accelerate RTL design optimization and design‑space exploration using AI‑based tools, agentic workflows, and automation frameworks.
Assist in testbench generation and corner coverage.
Improve debug efficiency across simulation and silicon learning loops.

Requirements

Master’s degree in electrical or computer engineering
Nice to have: DRAM design (DDR5, LPDDR5, HBM)
Nice to have: AI/ML‑assisted design flows
Nice to have: NAND memory design
Nice to have: SoC/ASIC semicustom flow

Skills

RTL design digital IP design microarchitecture AI‑based tools testbench generation simulation

DFT Lead Engineer

Broadcom · Posted Nov 3, 2026

Open

San Jose, California, United States
On-site
Full-time · Lead
$144K–$230K per year
10+ years

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Principal DFT Engineer responsible for leading DFT programs from chip level specification through implementation and verification for SoC DFT designs.

Compensation

The annual base salary range for this position is USD 143,800.00 To USD 230,000.00

Responsibilities

Understanding Broadcom & customer DFT feature requirements & DPPM goals & defining appropriate DFT specifications for the ASIC
Implementing DFT, including Scan, MBIST, TAP, LBIST, IO, SerDes and other I/P DFT integration
Working closely with STA and DI Engineers design closure for test
Generating, Verifying & Debugging Test vectors before tape release
Validating & Debugging Test vectors on ATE during the silicon bring up phase

Requirements

Bachelors in Electrical/Electronic/Computer Engineering
Masters Degree in Electrical/Electronic/Computer Engineering
Nice to have: DFT Compiler
Nice to have: Mentor TestKompress
Nice to have: TetraMax

Skills

TCL PERL RUBY PYTHON C++

DFT Lead Engineer

DFT Lead Engineer

Compensation

Responsibilities

Requirements

Skills

Benefits

DFT Engineer

Compensation

Responsibilities

Requirements

Skills

DFT Engineer

Compensation

Responsibilities

Requirements

Skills

Staff DRAM RTL Design Engineer

Responsibilities

Requirements

Skills

DFT Lead Engineer

Compensation

Responsibilities

Requirements

Skills

Benefits

Benefits

Benefits