- Hillsboro, Oregon, United States
- Senior
- $120K–$235K per year
- 5+ years
Senior Physical Design Verification Engineer
Compensation
Silicon Engineering IC4 - The typical base pay range for this role across the U.S. is USD $119,800 - $234,700 per year. There is a different range applicable to specific work locations, within the San Francisco Bay area and New York City metropolitan area, and the base pay range for this role in those locations is USD $160,200 - $261,000 per year.
Responsibilities
- Work closely with top level and block level Physical Design Engineers on analysis and fixes on LVS, DRC, ERC, Antenna, etc.
- Drive full chip integration for physical design verification, signoff and Tape‑outs on the leading‑edge technology nodes.
- Collaborating with clock, analog, integration team on definition, implementation, and verification of critical chip routing, power delivery, block integration and other aspects.
- Work with 3pIP and 1pIP teams for efficient and timely SOC‑IP handshake.
- Work with CAD team, tool vendors, foundry and other external partners to develop and validate new tools, flows, runsets, etc.
Requirements
- Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field
- Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field
- Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field
- Nice to have: BS/MS in Electrical or Computer Engineering/Electrical Engineering