- San Diego, California, United States
- Full-time
Design and implement advanced PLL IPs for AMD products, including architecture development, transistor-level circuit design, and verification flows.
Responsibilities
- Design complex PLL building blocks including architecture development and transistor-level circuit design
- Run pre-tapeout verification flows to confirm design meets performance, power, reliability and timing requirements
- Work closely with mask design engineers to deliver physical design and define production/bench-level test plans
- Lead and mentor junior engineers
Requirements
- Master's in Electrical Engineering
- Ph.D. in Electrical Engineering
- Nice to have: Digital PLL techniques
- Nice to have: TDC
- Nice to have: DSP