- San Jose, California, United States
- On-site
- Full-time · Entry
- $69K–$110K per year
The successful candidate will participate in SoC DFT implementation, verification, and debug activities, supporting phases of SoC DFT-related activities including test insertion, pattern generation, coverage improvement, and silicon debug.
Compensation
The annual base salary range for this position is USD 68,800.00 To USD 110,000.00
Responsibilities
- Assist with DFT implementation, including Scan, MBIST, TAP, and IO integration.
- Support ATPG vector generation, simulation, and verification at the ASIC/Chip level.
- Help debug test vectors before tape release and during ATE silicon bring-up.
- Work closely with senior engineers on STA and design closure for test.
- Automate DFT flows and scripts for improved engineering efficiency.
Requirements
- Bachelor's degree in Electrical Engineering
- Master's degree in Electrical Engineering
- Bachelor's degree in Computer Engineering
- Master's degree in Computer Engineering
- Nice to have: Professional experience in DFT domain is a plus
Skills
Benefits
- Medical
- dental
- vision plans
- 401(K) participation including company matching
- Employee Stock Purchase Program (ESPP)