Lead architectural definition and specification of next-generation ML compute IP and acceleration blocks for Google Cloud AI silicon.
Locations (2)
Tel Aviv, Israel, Israel
Haifa, Israel, Israel
Responsibilities
Lead architectural definition, modeling, and specification of next-generation, high-performance ML compute IP and acceleration blocks for Cloud AI silicon.
Own the ML IP architecture specification throughout the entire product lifecycle: concept exploration, cycle-accurate modeling, implementation, silicon bring-up, and production.
Partner closely with leading AI research and algorithm teams and software compiler teams to explore architectural trade-offs and define hardware requirements for emerging model architectures.
Drive comprehensive architecture studies, evaluating compute dataflows, numerical formats, sparsity, and specialized acceleration mechanisms such as key-value cache optimization.
Drive performance, latency, power efficiency, and silicon area projections across model topologies and workload configurations.
Requirements
Bachelor's degree in Computer Engineering, Electrical Engineering, Computer Science, or related field
Nice to have: Master's degree or PhD in Electrical Engineering, Computer Engineering, or Computer Science
Nice to have: 5 years of experience leading architectural definition and microarchitecture of AI/ML accelerators
Nice to have: experience with modern ML frameworks and compilers
Develop and enhance analytical performance models and simulation frameworks for AI accelerators, GPU architectures, and large-scale AI systems.
Compensation
Hardware Engineering IC4 - The typical base pay range for this role across the U.S. is USD $119,800 - $234,700 per year. There is a different range applicable to specific work locations, within the San Francisco Bay area and New York City metropolitan area, and the base pay range for this role in those locations is USD $160,200 - $261,000 per year.
Responsibilities
Develop and enhance analytical performance models and simulation frameworks for AI accelerators, GPU architectures, and large-scale AI systems.
Model end-to-end AI training and inference workloads, including compute kernels, attention, MoE, memory access patterns, and communication operations.
Evaluate new architectural features, compute and memory hierarchies, interconnects, and collective communication mechanisms to identify performance and efficiency improvements.
Perform workload mapping and parallelization analysis across tensor, pipeline, expert, data, and context parallelism strategies to optimize accelerator utilization and scalability.
Develop system-level performance models to evaluate throughput, latency, perf/W, and TCO across accelerator, rack, and cluster configurations.
Requirements
Master's Degree in Electrical Engineering, Computer Engineering, Mechanical Engineering, or related field
Bachelor's Degree in Electrical Engineering, Computer Engineering, Mechanical Engineering, or related field
JPL Postdoctoral Fellow - Photon Counting Detectors for Space Imaging Systems
Postdoctoral researcher specializing in silicon detector characterization and optimization for high performance space imaging applications, focusing on EMCCDs, sCMOS, and Skipper CCDs.
Compensation
The typical full time equivalent annual hiring range for this job in Pasadena, California. $83,820 - $83,820
Responsibilities
Develop state-of-the-art test methodologies to extract key performance metrics
Refine detector operating modes and optimize clocking and bias schemes
Analyze parameters such as read noise, dark current, charge transfer efficiency, gain stability, and single-photon sensitivity
Lead precision QE measurements and spectral response characterization
Lead camera system integration efforts using custom electronics and low-noise readout chains
Lead design and architecture of SSD and storage systems, driving innovation and feasibility of new product concepts.
Compensation
$153,000.00 - $351,000.00 a year
Responsibilities
Recognize and articulate innovative product concepts and SSD architectures
Maintain strong technical engineering relationships with customers, partner system architects and key technologists
Work with Micron technologists, design engineers and engineering teams to ensure successful implementation and feasibility demonstration of new product concepts
Develop new product architecture specifications
Help to choose concepts for feasibility demonstration
Talented engineer to join the CPU design team to drive performance verification and correlation between RTL and the performance model for a CPU based on RISC-V ISA.
Locations (2)
Austin, Texas, United States
Santa Clara, California, United States
Compensation
Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets.
Responsibilities
Join a team driving improvements in CPU microarchitecture, verify performance and correlate RTL against the performance model.
Collaborate closely with RTL engineers and core architects to meet performance goals, debug miscorrelation and verify performance features.
Draft performance testplans and develop targeted microbenchmarks to exercise performance features and expose bottlenecks.
Enhance tools and methodologies for performance analysis and correlation to improve development efficiency.
Use innovative techniques to optimize power, performance, and area while driving performance experiments and evaluating results.
Senior Silicon Design Engineer to co‑design the hardware‑software interface for AMD Instinct GPUs, modeling performance and power across the AI compute stack.
Locations (2)
San Jose, California, United States
Bellevue, Washington, United States
Responsibilities
Build performance and power models linking architectural decisions to real workload behavior
Evaluate hardware features and software API designs against AI training and inference targets
Write and optimize GPU kernels and compiler passes for microarchitectural characteristics
Work across the stack including Linux kernel DRM/GEM, ROCm runtime, IREE compiler, and AI frameworks like PyTorch and Triton
Leverage performance models to drive software optimization and hardware design feedback
Requirements
Bachelor's in Computer Science
Master's in Computer Science
Nice to have: Experience with AMD Instinct GPU architectures (MI300X, MI350X, MI355X)
Lead end-to-end AI workload optimization strategy, driving performance across AMD’s AI software stack.
Responsibilities
Set the technical vision and roadmap for workload optimization across the AI software stack
Lead the profiling, analysis, and tuning of large-scale models to ensure out-of-the-box performance on AMD hardware
Partner with top customers and hyperscalers to understand unique workload requirements and deliver tailored architectural wins and software optimizations
Collaborate across hardware architecture, compiler, and framework teams to influence future silicon features
Drive the development of advanced tools and frameworks for performance estimation, modeling, and automated reporting
Requirements
PhD or Master’s degree in Computer Science, Electrical Engineering, or related field
Nice to have: High-level technical leadership
Nice to have: AI frameworks (PyTorch, JAX, vLLM, SGLang)
ML Hardware AchitectGoogle · Tel Aviv, Israel+1 more
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