Standard Operating Procedures (SOP) development jobs

Test existing and new products
Build automation and tools to ship with confidence
Work closely with engineers, designers, and product managers
Use apps as a musician and report findings with clear steps and precise isolation

Requirements

Bachelor’s degree in Computer Science, Software Engineering, or equivalent practical experience
Nice to have: test automation frameworks such as XCUITest
Nice to have: automated testing
Nice to have: music theory and notation
Nice to have: MIDI

Skills

Python

Wireless System Engineer

Apple · Posted Nov 11, 2026

Open

Spain
On-site
Full-time · Staff

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Engineers help architect and design the best wireless products at Apple, focusing on achieving the best wireless performance for billions of users.

Responsibilities

Architect and design wireless products
Drive innovation in wireless organization

Requirements

Bachelors degree in Electrical Engineering
Bachelors degree in Telecommunication Engineering
Master degrees
PhD/Doctorate
Nice to have: Wi-Fi systems development

Skills

RF fundamentals Communication theory RF lab equipment usage Wi-Fi wireless standards Bluetooth wireless standards Matlab Python C C++

Internship - AIML Research

Apple · Posted Nov 11, 2026

Open

Zurich, Zurich, Switzerland
On-site
Internship · Intern

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Internship in Apple’s Artificial Intelligence and Machine Learning organization to conduct research, develop models, and publish findings.

Responsibilities

Collaborate with researchers, engineers, and program/project managers to tackle innovative challenges
Design and implement solutions for reasoning and efficient machine learning problems
Present work to AIML leadership and submit for publication

Requirements

Working toward an MSc/PhD degree in computer science, engineering, data science, applied mathematics, or equivalent
Nice to have: experience training large scale models

Skills

linear algebra statistics machine learning research publishing academic research PyTorch Jax CUDA

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FE STA Engineer

Apple · Posted Nov 11, 2026

Open

Haifa, Haifa District, Israel +1 more
On-site
Full-time · Mid
2+ years

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As an ASIC STA Engineer, you will have responsibilities spanning all aspects of SoC design in terms of timing. Key responsibilities include timing sign-off, STA and sign-off flow development, ownership of Full chip, IP, and block level timing constraints both for regular and custom timing requirements from synthesis to sign-off to achieve sign-off quality timing constraints.

Locations (2)

Haifa, Haifa District, Israel
Herzliya, Tel Aviv District, Israel

Responsibilities

timing sign-off
STA and sign-off flow development
ownership of Full chip, IP, and block level timing constraints
interact with RTL designer to understand design intent and clock structure
interact with CAD to understand and develop flow

Requirements

B.Sc / M.Sc in Electrical or Computer Engineering

Skills

ASIC design timing closure flow and methodology

FE STA Engineer

Apple · Posted Nov 11, 2026

Open

Haifa, Haifa District, Israel +1 more
On-site
2+ years

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ASIC STA Engineer responsible for timing sign-off, flow development, and constraint ownership across SoC design.

Locations (2)

Haifa, Haifa District, Israel
Herzliya, Tel Aviv, Israel

Responsibilities

Develop timing sign-off and STA flow
Own full chip, IP, and block level timing constraints
Collaborate with RTL, CAD, and Physical design teams
Generate and manage SDC constraints
Script in Tcl and Perl

Requirements

B.Sc / M.Sc in Electrical or Computer Engineering

Skills

ASIC design timing closure flow Timing constraints writing Primetime

Experienced GPU Electrical Analysis Engineer

Apple · Posted Nov 11, 2026

Open

Cambridge, England, United Kingdom +1 more
On-site

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Design and manufacture next-generation, high-performance, power-efficient GPUs for Apple products and services.

Locations (2)

Cambridge, England, United Kingdom
London, England, United Kingdom

Responsibilities

Realize complete electrical analysis closure from early design planning to tapeout
Design power grid specifications balancing power integrity targets and PNR performance
Define on-die power switch topology, wake-up schemes, and in-rush control
Collaborate on bump map, custom RDL routing, and package design/optimization
Develop test structures, procedures/automation, and analysis methodologies for electrical analysis challenges

Requirements

Bachelor's or Master's in Electrical Engineering
Nice to have: On-die high frequency power delivery
Nice to have: Bump planning and redistribution layer routing strategies

Experienced GPU Electrical Analysis Engineer

Apple · Posted Nov 11, 2026

Open

Cambridge, England, United Kingdom +1 more
On-site
Full-time · Senior

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As part of our Silicon Technologies group, you’ll help design and manufacture our next-generation, high-performance, power-efficient GPU.

Locations (2)

Cambridge, England, United Kingdom
London, England, United Kingdom

Responsibilities

Realizing the complete electrical analysis closure from early design planning to tapeout
Design power grid specification that achieves the best balance between power integrity targets and PNR performance, power and Area (PPA)
Involved with the definition of on-die power switch topology, wake-up schemes, and in-rush control
Collaborate with internal teams to drive bump map, custom RDL routing, and package design/optimization
Develop test structures, procedures/automation, and analysis methodologies for electrical analysis challenges

Requirements

BS/MS in EE
Nice to have: On-die high frequency power delivery

SoC Physical Design Engineer

Apple · Posted Nov 11, 2026

Open

Munich, Bavaria, Germany
On-site
Full-time · Senior

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Take part in the large scale SoC physical design cycle from netlist to tape-out, including full flow of back-end implementation and verification always meeting schedule and design goals.

Responsibilities

Own block level PnR, floor-planning, clock and power distribution
Get involved with static timing closure with commercial tools
Do power & noise analysis (EM/IR-Drop/Xtalk) as well as layout verification (DRC/LVS)
Develop and validate dedication low power clock network guidelines
Resolve design and flow issues related to physical design and identify potential solutions

Requirements

MSEE or equivalent strong experience
Nice to have: Verilog
Nice to have: Hierarchical design approach
Nice to have: Top-down design
Nice to have: RC extraction and correlation

Skills

Physical Design PnR Static Timing Analysis Clock/Power Distribution DRC/LVS EM/IR-Drop/Xtalk analysis

Facilities Coordinator

Apple · Posted Nov 11, 2026

Open

London, England, United Kingdom
On-site

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Supports day‑to‑day delivery of facility services across Apple’s London office.

Responsibilities

Provide front‑line support across maintenance, vendor coordination, and employee‑facing facilities services
Build a strong operational foundation while contributing to a team that supports every Apple employee and customer

Requirements

Nice to have: work order systems
Nice to have: vendor coordination
Nice to have: contractor scheduling

Skills

facilities management property management coordination maintenance vendor coordination basic reporting data entry

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