Electronics Engineer I
JPL/NASA · Pasadena, US· On-site · Full-time · Entry
Low Power Verification Engineer, Physical Design
Google · Sunnyvale, US· On-site
Sr. Physical Design Engineer
Qualcomm · Santa Clara, US· Senior
Director, Payload Electronics, Space Communications Systems
E-Space · Santa Clara, US+1 more · Full-time · Manager
ASICS Design Engineer, Senior
Qualcomm · Hsinchu City, TaiwanOn-site · Senior
ASICS Design Engineer, Staff
Qualcomm · Hsinchu City, TaiwanOn-site · Full-time · Staff
Field Applications Engineer
Lattice Semiconductor · San Jose, US+1 more
Electrical Engineer III/IV
Crane Company · Burbank, US· Senior
Electrical Engineer II
Crane Company · Lynnwood, US· On-site · Full-time · Mid
Senior Engineer (Level 1)- FPGA Design
Arrow Electronics, Inc. · Noida, IndiaFull-time · Senior
+10K new in the last hour
JPL/NASA · Posted Nov 5, 2026
First 2 pages free · sign up to see every job
Design and develop electronics for space and terrestrial robotics, including analog, digital, and power circuits, simulation, PCB design, and testing.
Own technical development of electronics, including specification, architecture, simulation, PCB design, laboratory testing, and mission infusion Design analog, digital, and power electronics circuits for space and terrestrial robotics Identify candidate technologies, design test fixtures, and support heavy ion testing to evaluate new parts for radiation effects Collaborate with JPLers across disciplines to integrate your designs into complex robotic missions and instrument systems Dream up and propose new projects to solve the hardest problems in space and on earth Bachelor’s degree in electrical engineering, robotics engineering, or similar technical discipline Nice to have: lead new hardware projects Nice to have: propose new electronics projects Nice to have: win funding Nice to have: single board computer design health, dental, vision, wellbeing, retirement plans paid time off learning rideshare childcare Google · Posted Nov 10, 2026
Design and verify low‑power ASICs for Google’s TPU architecture, developing testbenches, simulation environments, and power‑analysis workflows.
US: $163000 - $236000 (USD) + 15% bonus target + equity + benefits
Define low power verification strategies and methodologies for complex ASIC designs. Author comprehensive low power verification plans targeting UPF‑defined power domains and states. Develop power‑aware testbenches and simulation environments using SystemVerilog and UVM. Verify power intent utilizing static low power verification tools like VC LP or Conformal LP. Run gate‑level simulations with power‑aware models to validate power‑up and power‑down sequences. Nice to have: low‑power digital design Nice to have: advanced process nodes Nice to have: Verilog Nice to have: VHDL Nice to have: SystemVerilog Qualcomm · Posted Nov 9, 2026
Lead ASIC design, verification, and validation for high‑performance, low‑power products.
$134,500.00 - $201,700.00
Define, model, design, optimize, verify, validate, implement, and document IP (block/SoC) development Create architectures, circuit specifications, logic designs, and system simulations Collaborate across teams to develop and execute implementation strategies Evaluate process flow from design to synthesis, place and route, timing, power use, and verification Utilize tools/applications such as RTL to GDS Flow and Virtuoso Bachelor's degree in Science, Engineering, or related field Master's degree in Science, Engineering, or related field PhD in Science, Engineering, or related field Nice to have: Master's degree in Electrical/Electronic Engineering, Computer Engineering, or Computer Science Nice to have: 3+ years ASIC design experience E-Space · Posted Nov 10, 2026
Lead the design, development, and production of payload electronics for low Earth orbit space systems.
Santa Clara, California, United States Arlington, Texas, United States The target base pay for this position is $200,000 - $290,000 annually.
Design and architect signal‑chain and RF front‑end for space payloads Develop and validate beamforming and digital signal processing algorithms Lead hardware design, qualification, and production ramp Coordinate interfaces with spacecraft bus, antenna, and software teams Manage engineering team, hiring, development, and performance Bachelor's degree in electrical engineering, physics or related field Nice to have: 5G NR Nice to have: Non‑Terrestrial Networks Nice to have: advanced degree in electrical engineering or physics Qualcomm · Posted Nov 9, 2026
Lead ASIC design and delivery for Ethernet switch subsystems, driving architecture-aligned implementation, optimization, and integration.
Implement RTL design, synthesis, and timing closure for networking datapath/control logic Participate in SoC integration with focus on Ethernet switch subsystems Lead design and delivery of key subsystems in Ethernet switch ASICs Own micro-architecture and RTL design of networking blocks Drive subsystem integration, performance tuning, and power optimization Bachelor's degree in Science, Engineering, or related field Master's degree in Science, Engineering, or related field PhD in Science, Engineering, or related field Qualcomm · Posted Nov 9, 2026
Implement RTL design, synthesis, and timing closure for networking datapath/control logic for Ethernet switch ASICs.
Implement RTL design, synthesis, and timing closure for networking datapath/control logic. Participate in SoC integration with focus on Ethernet switch subsystems. Lead design and delivery of key subsystems in Ethernet switch ASICs, driving architecture-aligned implementation and optimization. Own micro-architecture and RTL design of networking blocks (e.g., forwarding engine, parser, traffic manager). Drive subsystem integration, performance tuning, and power optimization. MS/BS in EE (MS preferred) Bachelor's degree in Science, Engineering, or related field Master's degree in Science, Engineering, or related field PhD in Science, Engineering, or related field Nice to have: merchant silicon Lattice Semiconductor · Posted Aug 17, 2026
San Jose, California, United States Seattle, Washington, United States Identify and develop new opportunities within accounts. Give product presentations to the customer describing how Lattice products provide the optimum solution for their application. Give product demonstrations and execute benchmarks to show product capabilities and ease of use. Provide technical support to customers in their selection and use of Lattice silicon products, development tools, IP, and solutions stack. Provide technical leadership and guidance that focuses on design win strategies for all customer opportunities. BS in Electrical Engineering, Computer Engineering, or Computer Science. MS or PhD Crane Company · Posted Oct 22, 2026
Senior electrical engineer responsible for designing, developing, and mentoring in aerospace and electronics products.
Electrical Engineer III: $129,800 - $152,100
Electrical Engineer IV: $156,200 - $183,300
Work effectively with all functional groups to achieve product performance and cost targets. Build quality and manufacturability into the design. Define and comply with company and regulatory guidelines. Support continuous process improvement activities. Plan, estimate, prioritize, and manage work activities to support project schedules and budgets. BA or BS Degree in an engineering discipline Masters or PhD preferred Crane Company · Posted Aug 24, 2026
Electrical Engineer II works with minimal supervision to research, plan, design, and develop products for the aerospace or electronics marketplace.
Salary range: $102,160.10 - $119,330.50. Several factors contribute to actual salary, including experience in a similar role or performing comparable job responsibilities, skills, training, and other qualifications. Some roles may be eligible for participation in performance-based bonus programs.
Work effectively with all functional groups to achieve product performance and cost targets. Build quality and manufacturability into the design. Support continuous process improvement activities including Kaizen, 5S practices. Demonstrate proficiency with verbal and written English for technical reports, presentations, analyses, or other communications. Understand, decompose, and define product and process requirements to support product development, sustaining and R&D. BA or BS Degree in an engineering discipline Masters or PhD preferred Arrow Electronics, Inc. · Posted Dec 19, 2024
Senior Engineer responsible for FPGA/ASIC design, development, simulation, testing, debugging, verification and validation for embedded data acquisition applications.
Design, develop, simulate, test and debug FPGA/ASIC designs Perform coding in Verilog, VHDL, System Verilog Verify and validate embedded data acquisition applications
Competitive annual discretionary bonus program RSU grants Comprehensive benefits package
Nice to have: experience with space flight electronics Competitive salaries Health and wellness care options Paid holidays Paid time off Continuous learning and development
healthcare retirement plans paid time off
Health care, dental, vision, life and disability insurance 15 days of paid time off 12 paid holidays per year 401k plan with company match Education Reimbursement
Electronics Engineer INewJPL/NASA · Pasadena, US
Low Power Verification Engineer, Physical DesignNewGoogle · Sunnyvale, US
Sr. Physical Design EngineerNewQualcomm · Santa Clara, US
Director, Payload Electronics, Space Communications SystemsE-Space · Santa Clara, US+1 more