As a Wireless SOC Design Verification Engineer, you'll be at the heart of the chip design effort — owning a meaningful verification scope and growing it project to project. You'll work alongside DV methodologists, designers, architects, communication systems engineers, and firmware engineers to build reusable testbenches and verification environments using the latest metric-driven verification methodology.
Responsibilities
Pre-silicon RTL verification at the block, subsystem, and top-level SOC, taking your scope from test planning through coverage closure and signoff.
Focus at block level, subsystem level, or top-level SOC, including end-to-end simulations of the entire data/control path.
Build reusable testbenches and verification environments using the latest metric-driven verification methodology.
Serve as the primary technical resource for the verification team, leading end-to-end verification of IPs and their integration using best-in-class methodologies.
Responsibilities
Serve as the primary technical resource for the verification team, providing expert guidance.
Act as the central liaison to other verification and methodology teams at Infineon to coordinate strategies and resolve issues centrally
Lead and execute end-to-end verification of IPs and their integration using best-in-class methodologies (e.g., formal verification, AI-assisted testing)
Lead and review the third-party’s verification methodology and execution, from planning through implementation to final sign-off
Drive vendor accountability to close gaps and meet milestone targets
Requirements
Bachelor’s or master’s degree in electrical engineering, Computer Engineering, Computer Science, or a related technical field
Lead verification architecture, planning, and execution for complex FPGA, programmable SoC, and infrastructure-class subsystems, including block, subsystem, and full-chip verification.
Compensation
$231,500 - $330,000 USD
Responsibilities
Lead verification architecture, planning, and execution for complex FPGA, programmable SoC, and infrastructure-class subsystems
Define comprehensive verification plans that translate architectural intent and product requirements into measurable functional, performance, resilience, and coverage objectives
Architect and develop scalable, reusable SystemVerilog/UVM verification environments, verification IP, scoreboards, reference models, constrained-random stimulus, checkers, and coverage models
Establish and advance verification methodology, coding standards, testbench guidelines, regression practices, and automation that improve consistency, quality, reuse, debug efficiency, and predictability across programs
Drive verification closure using functional, code, assertion, and cross coverage; identify coverage gaps, evaluate risk, and ensure readiness against defined exit criteria
Requirements
Bachelor’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical discipline
Provide provide technical leadership and execute FPGA verification activities for mission-critical aerospace and defense products, including simulation development, regression execution, hardware integration, and laboratory testing supporting DO-254 compliance.
Responsibilities
Provide hands-on technical leadership for FPGA verification, including verification planning, testbench development, simulation, regression testing, hardware testing, and results analysis.
Develop, maintain, and execute verification environments using VHDL, Verilog, SystemVerilog, Universal Verification Methodology (UVM), and assertion-based verification.
Review requirements for clarity, completeness, and verifiability; develop requirements-based verification procedures and maintain traceability between requirements, tests, and results.
Support DO-254 verification activities, including preparation and review of verification plans, procedures, results, coverage analyses, and supporting lifecycle documentation.
Develop and enhance scalable simulation environments, automated regressions, and scripting infrastructure to improve verification efficiency and repeatability.
In this position you will own the verification strategy, testbench development, and sign-off readiness for assigned IPs, subsystems, or distributed systems.
Own the verification planning process for assigned IPs and subsystems, including definition of verification scope, strategy, coverage goals, and resource requirements
Develop and maintain reusable verification environments, testbenches, verification components, and infrastructure using industry-standard methodologies and languages
Ensure complete verification of functional requirements through directed, constrained-random, assertion-based, and coverage-driven verification
Execute verification closure activities by tracking functional, code, assertion, and other relevant coverage metrics against defined project targets
Identify, analyze, and drive resolution of design defects through systematic debug and root-cause analysis in collaboration with design engineering teams
Requirements
Bachelor's or Master's degree in Electrical Engineering, Electronics Engineering, Computer Engineering, or a related technical discipline
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