Architects, designs, implements, verifies, and optimizes performance and power of GPU cores.
Compensation
$141,300.00 - $211,900.00
Responsibilities
Owning and executing on key independent tasks towards program requirements
Using verbal and written communication skills to convey basic, routine factual information about day-to-day activities to others who are fully knowledgeable in the subject area
Working within prescribed timeline requirements and resource constraints
Applying independent creative thought to troubleshoot technical problems or deal with novel circumstances
Research through available resources and engagement with various inter-disciplinary teams
Requirements
Bachelor's degree in Computer Engineering, Computer Science, Electrical Engineering, or related field
Master's degree in Computer Engineering, Computer Science, Electrical Engineering, or related field
PhD in Computer Engineering, Computer Science, Electrical Engineering, or related field
Lead the functional verification of complex ASIC designs for AI fabric switches, managing the full verification lifecycle and collaborating with software and system validation teams.
Compensation
The base salary range is USD 185,000.00 – USD 240,000.00.
Responsibilities
Plan and write verification tests using System Verilog/UVM/C/C++
Validate power management architectures and features for Intel's next-generation SoC products, develop validation strategies, execute test plans, and debug complex design issues.
Locations (3)
Folsom, California, United States
Santa Clara, California, United States
Hillsboro, Oregon, United States
Compensation
Annual Salary Range for jobs which could be performed in the US: $164,470.00-269,100.00 USD
Responsibilities
Develop and execute comprehensive validation plans
Design, develop, and maintain validation environments and automated test content
Validate power management features such as DVFS, power gating, clock gating, low‑power states, reset flows, thermal management, and telemetry
Develop validation content using SystemVerilog, UVM, simulation, and emulation platforms
Senior Emulation Engineer on the AISiE SoC Design Verification team, developing scalable verification environments for AI accelerators.
Compensation
Silicon Engineering IC4 - The typical base pay range for this role across the U.S. is USD $119,800 - $234,700 per year. There is a different range applicable to specific work locations, within the San Francisco Bay area and New York City metropolitan area, and the base pay range for this role in those locations is USD $160,200 - $261,000 per year.
Responsibilities
Build, validate and automate emulation models with constant improvement in runtime efficiency.
Collaborate with architects and design engineers to define verification plans, including strategy, test environments, and requirements for IP/Subsystem/SoC-level verification.
Develop reusable verification components, including monitors, trackers, debug flows, assertions, and functional coverage models.
Triage and debug failures across testbenches, simulation, and emulation environments.
Develop Makefiles and automation scripts to enable scalable and efficient verification flows.
Requirements
Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field
Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field
Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field
As a Design Verification Engineer specializing in Emulation, you will be responsible for developing and executing verification strategies to ensure the correctness and performance of complex hardware designs. Your primary focus will be on emulation platforms to accelerate verification cycles and improve coverage.
Responsibilities
Develop and implement verification plans and test benches using emulation tools and methodologies.
Collaborate with design and validation teams to identify verification requirements and coverage goals.
Utilize emulation platforms to run large-scale verification tests and debug design issues.
Analyze verification results, identify bugs, and work closely with design engineers to resolve issues.
Maintain and enhance verification infrastructure and automation frameworks.
Architects, designs, implements, verifies, and optimizes performance and power of GPU cores.
Compensation
$135,700.00 - $203,500.00
Responsibilities
Owning and executing on key independent tasks towards program requirements
Using verbal and written communication skills to convey basic, routine factual information about day-to-day activities to others who are fully knowledgeable in the subject area.
Working within prescribed timeline requirements and resource constraints
Applying independent creative thought to troubleshoot technical problems or deal with novel circumstances.
Research through available resources and engagement with various inter-disciplinary teams
GPU Design Verification Engineer, SeniorNewQualcomm · San Diego, US
Principal Design Verification Engineer (AI Fabric Switches)Astera Labs · San Jose, US
ASIC EngineerCisco · Bangalore, India
ASIC EngineerCisco · Bangalore, India