Lead verification across block, subsystem, and multi-FPGA system-level designs, collaborating with hardware designers and embedded software engineers to deliver fully verified, high-performing, and trusted systems.
Compensation
Salary: £90,000 to £115,000 DOE + Bonus + Benefits
Responsibilities
Own the strategy and execution for block-level, subsystem, and multi-FPGA system designs
Develop scalable UVM-based testbenches that push the boundaries of performance across multiple FPGAs and configurations
Drive verification efforts with a sharp focus on risk, coverage, and system-level behaviour
Make pragmatic trade-offs to maintain world-class quality while keeping pace with innovation
Requirements
Nice to have: Formal verification
Nice to have: Mentoring junior verification engineers
Perform board-level and system-level debugging and analyze customer-reported issues and identify root causes.
Design and develop enterprise server motherboards and add-on card products, including schematic capture, BOM creation, debugging, and product validation.
Review PCB layouts and collaborate with layout engineers to ensure design quality, manufacturability, and compliance with hardware design guidelines.
Prepare and maintain engineering documentation, including product specifications, BOMs, validation reports, test procedures, and debugging guides.
Perform design verification testing (DVT), system validation, and qualification testing to ensure products meet engineering specifications and customer requirements.
Requirements
Bachelor's degree in Electrical Engineering or Computer Engineering; Master's degree is a plus.
Lead platform deployment, availability, and stability for data center CPU/GPU systems, driving system-level debugging and continuous improvement in a fast-paced on-site environment.
Responsibilities
Manage platform deployment, availability, and stability for data center CPU/GPU systems
Lead system-level debugging efforts involving hardware, firmware, Linux, networking, power, and thermal behavior
Develop structured debug strategies, validation flows, and failure-analysis methodologies
Installation, configuration of various OS Distros from console, setup Network gear, perform and validate Network configurations
Provide logs and statistics that will help in further debug of issues
Requirements
Bachelor's or Masters degree in electrical or computer engineering/ Computer science
Own calibration across Calder's robot and egocentric capture systems for APAC, focusing on camera intrinsics, extrinsics, stereo, camera–IMU, and hand–eye transforms.
Responsibilities
Own multi-sensor calibration end to end across rigs and egocentric setups in APAC — camera intrinsics/extrinsics, stereo, camera–IMU, and camera–arm / eye-in-hand / eye-to-hand transforms
Use robot arms to make calibration repeatable: plan and program pose trajectories that sweep targets and sensors through full coverage, automate capture and solve, and take operator-to-operator variance out of the result
Define and hold calibration quality bars — reprojection error, coverage, observability, run-to-run repeatability — and gate captures on them
Design and operate egocentric calibration setups (boards, poses, lighting, mounts, capture procedures) so they are repeatable and produce production-quality results
Diagnose calibration and tracking failures from real captures — sync, coverage, board detection, extrinsics drift, kinematic error — and close the loop into procedure and software
Lead the development, implementation, and verification of advanced signal‑processing algorithms for high‑performance communication systems in space vehicles.
Compensation
$145,000 - $185,000 / year
Responsibilities
Design, implement, and optimize DSP algorithms for advanced communication systems
Develop and refine symbol timing recovery, carrier recovery, and equalization algorithms
Perform fixed‑point modeling, quantization analysis, and algorithm optimization for hardware deployment
Use MATLAB and Simulink for modeling, simulation, and verification of DSP processing chains
Collaborate closely with FPGA design teams to translate algorithms into hardware‑efficient architectures
Requirements
Master's degree in Electrical Engineering or related field
Nice to have: PhD in Electrical Engineering or related field
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