- Manila, Philippines
- Senior
Senior Design Engineer – Modeling position develops, validates, and delivers IP behavioral models and related hardware collateral used by internal engineering teams and software-facing customers.
Responsibilities
- Develop and maintain IP functional and behavioral models using Verilog, SystemVerilog, and, where applicable, SystemC and C++.
- Translate IP specifications, schematics, RTL, and design intent into clear model requirements, implementation plans, and verification objectives.
- Perform functional testing, audits, lint and CDC checks, regression testing, and consistency or equivalency checks against approved hardware references and specifications.
- Lead or support the generation, audit, validation, and release of timing, power, signal-integrity, configuration, and metadata deliverables used for hardware and software integration.
- Investigate and resolve model behavior, hardware-to-software integration, and customer-facing issues across the IP development lifecycle.
Requirements
- Bachelor’s or Master’s degree in Electrical Engineering, Electronics Engineering, Computer Engineering, or a related field
- Nice to have: timing
- Nice to have: power
- Nice to have: IBIS
- Nice to have: signal-integrity