Referso Jobs

Work within an analog/mixed-signal design team based in Valencia, Spain, and other locations worldwide
Work closely with cross-functional teams to define, implement and introduce products to customers
Support development of medium and high-complexity ICs from architecture selection to implementation and debug
Perform mixed-mode IC top-level/block design, transistor-level circuit design and simulation
Use recommended design and verification techniques, tools & flows to produce efficient designs

Requirements

B.E., M.S. or Ph.D. in Electrical Engineering

Skills

analog/mixed-signal design fine-line CMOS DACs ADCs bandgaps bias circuits LDOs

Analog Design Architect

onsemi · Posted Nov 5, 2026

Open

Cork, Co. Cork, Ireland
On-site
Full-time · Senior
8–15 years

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Lead analog IP architecture, strategy, and roadmap development for the Treo BCD65 platform, mentoring junior engineers and integrating AI tools.

Responsibilities

Define and evolve architecture and technical strategy for power, clock, monitoring and reset IP
Engage product-line teams to understand needs and constraints
Translate product and platform needs into IP architecture requirements and roadmaps
Lead architectural trade‑off studies across performance, power, area, robustness, testability and integration complexity
Champion reusable IP and consistent interfaces

Requirements

Bachelor's degree in electrical or electronic engineering or closely related discipline
Master's degree in a relevant discipline
Nice to have: Experience in BCD technologies, particularly BCD65
Nice to have: Supply and voltage monitoring
Nice to have: Power‑on reset

Skills

Analog IC design Bandgap references LDOs DC–DC regulators Oscillators

Experienced Analog IC Designer

onsemi · Posted Nov 5, 2026

Open

Cork, Munster, Ireland
11–15 years

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Lead the design, development, and production of analog IP for the Treo BCD65 platform, including architecture definition, block development, verification, and mentoring of junior engineers.

Responsibilities

Define architectures for power, clock, monitoring and reset IP
Translate product-line requirements into IP specifications and roadmaps
Drive architecture trade-offs across performance, power, area, robustness, testability and integration complexity
Champion reusable IP architectures and interfaces
Communicate architecture proposals, roadmap priorities and technical decisions

Requirements

Bachelor's in electrical or electronic engineering
Master's in a relevant discipline
Nice to have: BCD technologies
Nice to have: scripting
Nice to have: design-flow automation

Skills

bandgap references LDOs DC–DC regulators oscillators PLLs analog circuit fundamentals

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