Lead digital hardware design, review, and debug for Intel processor-based platforms, providing technical support and training to customers across India.
Responsibilities
Support board-level digital hardware design and conduct detailed design reviews for customer products based on Intel Core and Atom processors
Review customer schematics against Intel Platform Design Guides and identify potential design issues
Review processor interfaces and associated circuitry including DDR, PCIe, USB, SATA, DisplayPort, Ethernet, I2C/SMBus, SPI, UART, GPIO and platform control signals
Review multilayer PCB stack-up and board layout implementation for processor-based platforms
Perform detailed schematic and layout reviews of high-speed digital interfaces
Requirements
Bachelor's or Master's degree in Electronics/Electrical Engineering or a related discipline
Nice to have: experience with Intel Core or Atom processors
Nice to have: embedded and Edge compute designs such as COM Express, COM-HPC, 3.5-inch SBC, Mini-ITX
Nice to have: DDR4/DDR5/LPDDR memory design
Nice to have: high-speed interface experience such as PCIe Gen4/Gen5, USB 3.x/USB4, DisplayPort
Join AMD’s dynamic Systems Development team to bring cutting-edge servers and switch solutions to life, focusing on SoC, board, and system-level integration-leading validation and new product introduction (NPI) qualification.
Responsibilities
Lead Switch System bring-up, System Rack Validation, and NPI qualification for server and switch hardware with OEM vendors.
Drive deployment and sustaining efforts for hardware solutions through all compliance stages.
Lead debug and root cause analysis of deployed systems by reviewing board layouts and schematics.
Collaborate cross-functionally with internal engineering teams and external partners to ensure timely delivery and quality standards.
Gather system feature requirements, define detailed test plans, and execute hardware validation plans.
Requirements
Bachelor’s or master’s degree in electrical engineering
Computer Engineering, or related field
Nice to have: Cadence schematic and board layout tools
Design, integrate, and validate FPGA-based systems for next‑generation SSD and storage technologies.
Compensation
40.000,00 € - 69.000,00 € per year
Responsibilities
Define and develop system architectures for FPGA-based SSD and storage validation platforms.
Architect, integrate, and configure complex FPGA subsystems, including PCIe, DMA, memory, embedded processors, high‑speed interfaces, control, monitoring, and debug functionality.
Drive system‑level integration, bring‑up, validation, and root‑cause analysis across FPGA hardware, embedded firmware, host software, storage devices, and PCIe, NVMe, and UFS protocols.
Perform system and protocol‑level debugging using FPGA embedded instrumentation, protocol analyzers, oscilloscopes, logic analyzers, and other lab equipment.
Collaborate with firmware, silicon, validation, and product engineering teams to define system requirements, interfaces, architectures, validation strategies, and develop technical documentation.
Requirements
Master’s degree in Electronic Engineering, Computer Engineering, or a related field
Lead BIOS firmware development for workstation platforms, collaborating with internal and outsourced partners, defining design guidelines, and integrating new technologies.
Responsibilities
Collaborate with firmware and hardware teams to design and develop BIOS firmware
Define and enforce design guidelines and standards
Integrate new technologies and frameworks into firmware
Develop and maintain design specifications and documentation
Lead testing, debugging, and validation of firmware
Requirements
Bachelor’s degree in computer science, information systems, electrical engineering, or equivalent
Join the DCS PCIe Product Marketing team supporting broad, reusable semiconductor product strategy, requirements, market intelligence, customer adoption, technical ecosystems, launches, roadmaps, and organizational capability.
Responsibilities
Define PCIe product, market, application, customer, positioning, validation, go-to-market, launch, and lifecycle approaches across products.
Define broad product, system, software, hardware, business, market, and ecosystem requirements within approved scope focused on PCIe Data Center trends and technologies.
Lead a globally distributed engineering organization spanning design, verification, physical design, DFT, and silicon validation across multiple sites to deliver advanced connectivity silicon products.
Expected Base Pay Range (USD) 242,080 - 362,600, $ per annum
Responsibilities
Lead a globally distributed engineering organization spanning design, verification, physical design, DFT, and silicon validation across sites including Irvine, Santa Clara, Ottawa, Pavia, Aachen, Bucharest, Vietnam, and India
Own end-to-end execution of one or more major product families — from RTL design through tape-out, bringup, and production release
Drive first-silicon success across next-generation 200G/lane and beyond connectivity products on 3nm and 2nm process nodes
Establish and continuously improve design flows, verification methodologies, DFT strategies, and emulation infrastructure to accelerate delivery and quality
Partner with architecture, systems, and product management teams to define the technical roadmap for next-generation connectivity products
Requirements
BS/MS/PhD in Electrical Engineering, Computer Engineering, or related field
Hardware Engineer, Networking Switch Bring Up and Rack Level Performance ValidationNewAdvanced Micro Devices, Inc · Santa Clara, US
Senior Embedded Linux EngineerNewTYTAN Technologies GmbH · Munich, Germany
GPU Platform SME (AI Infrastructure Validation)NewLenovo · Morrisville, US