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1–5 jobs· newest first

FPGA SW Validation Engineer (PR)New
Altera · Bengaluru, India
Full-time · Senior
Physical Design Engineer
Apple · Texas, US+4 more
On-site
Physical Design Engineer
Apple · Texas+4 more
On-site
Physical Design Engineer
Apple · Texas, US+4 more
On-site
Physical Design Engineer
Apple · Texas, US+4 more
On-site

+10K new in the last hour

FPGA SW Validation Engineer (PR)

Altera · Posted Nov 11, 2026

Bengaluru, Karnataka, India
Full-time · Senior
6+ years

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Validates and researches compiler optimizations, partial reconfiguration flow, and debugging features for Altera FPGA hardware.

Responsibilities

Validates and researches compiler optimizations, partial reconfiguration flow, and debugging features like SignalTap & System Console using Quartus Design Software and Altera FPGA hardware
Creates designs using HDLs and Altera IPs and verifies them for functionality and timing on Altera FPGA hardware boards
Regresses designs during each release for QoR and monitors performance over targeted FPGA devkits
Collaborates with cross-functional teams to develop and improve validation strategies and resolve customer issues

Requirements

Master's/Bachelor's Degree in Electronics/VLSI/Digital Design or other related disciplines

Skills

FPGA/Digital Logic Design RTL/HDL design and verification using VHDL, Verilog or SystemVerilog FPGA Devices like Agilex, Virtex Altera Quartus Xilinx Vivado Synplify QuestaSim VCS XCelium STA Hardware validation of FPGA designs Unix/Linux Shell scripting Perl/TCL Python scripting PCIe Ethernet Avalon bus protocols AHB AXI HPS High-Speed interfaces Quartus Vivado Shell Python

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Physical Design Engineer

Apple · Posted Nov 5, 2026

Texas, United States +4 more
On-site
10+ years

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Physical Design Engineer

Locations (5)

Texas, United States
California, United States
Beaverton, Oregon, United States
Melbourne, Florida, United States
Waltham, Massachusetts, United States

Responsibilities

Contribute to all phases of physical design of high performance PHY design from RTL to delivery of our final GDSII

Physical Design Engineer

Apple · Posted Nov 5, 2026

Texas, United States +4 more
On-site
10+ years

Apply with RefersoAI Apply on careers page

Physical Design Engineer

Locations (5)

Texas, United States
California, United States
Beaverton, Oregon, United States
Melbourne, Florida, United States
Waltham, Massachusetts, United States

Responsibilities

Contribute to all phases of physical design of high performance PHY design from RTL to delivery of our final GDSII

Physical Design Engineer

Apple · Posted Nov 5, 2026

Texas, United States +4 more
On-site
10+ years

Apply with RefersoAI Apply on careers page

Physical Design Engineer

Locations (5)

Texas, United States
California, United States
Beaverton, Oregon, United States
Melbourne, Florida, United States
Waltham, Massachusetts, United States

Responsibilities

Contribute to all phases of physical design of high performance PHY design from RTL to delivery of our final GDSII

Physical Design Engineer

Apple · Posted Nov 5, 2026

Texas, United States +4 more
On-site
10+ years

Apply with RefersoAI Apply on careers page

Physical Design Engineer

Locations (5)

Texas, United States
California, United States
Beaverton, Oregon, United States
Melbourne, Florida, United States
Waltham, Massachusetts, United States

Responsibilities

Contribute to all phases of physical design of high performance PHY design from RTL to delivery of our final GDSII

Requirements

Bachelor's of Science in Electrical Engineering
Nice to have: High PHY
Nice to have: SOC designs
Nice to have: Physically aware synthesis
Nice to have: Basic SoC Architecture

Skills

Physical Design PHY design CAD Timing Logic design GDSII Floor-planning Place & Route Power-grid Clock specifications Physical Verification SoC Architecture HDL languages Verilog Physical Design & Synthesis tools Perl/Tcl Extraction STA methodology LVS/DRC

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Requirements

Bachelor's of Science in Electrical Engineering
Nice to have: deep design experience in high PHY and/or SOC designs
Nice to have: knowledge of industry standards and practices in Physical Design
Nice to have: deep understanding of scripting languages
Nice to have: deep understanding of Physical Design Verification methodology

Skills

CAD timing logic design RTL GDSII floor-planning place & route power-grid clock specifications physical verification LVS/DRC HDL Verilog Perl/Tcl extraction STA methodology Power-grid tools STA tools

See full job description

Requirements

Bachelor's of Science in Electrical Engineering
Nice to have: High PHY and/or SOC designs
Nice to have: Physical Design standards and practices
Nice to have: Physical Design Verification methodology

Skills

Physical Design PHY design CAD Timing Logic design GDSII Floor-planning Place & Route Power-grid Clock specifications Physical Verification SoC Architecture HDL languages Verilog Power user of industry standard Physical Design & Synthesis tools Perl/Tcl Extraction STA methodology LVS/DRC Perl Tcl STA tools LVS/DRC tools

See full job description

Requirements

Bachelor's of Science in Electrical Engineering
Nice to have: High PHY and/or SOC designs
Nice to have: Deep Knowledge about industry standards and practices in Physical Design
Nice to have: Deep Understanding of scripting languages
Nice to have: Solid understanding of Extraction and STA methodology and tools

Skills

Physical Design PHY design CAD Timing Logic design GDSII Floor-planning Place & Route Power-grid Clock specifications Physical Verification SoC Architecture HDL languages Verilog Power user of industry standard Physical Design & Synthesis tools Perl/Tcl Extraction STA methodology LVS/DRC

See full job description