Referso Jobs

FPGA Engineer

Sky Spy Inc · Posted Nov 8, 2026

Open

Munich, Bavaria, Germany
Hybrid
Full-time · Senior
5+ years

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FPGA Engineer

Sky Spy Inc · Posted Nov 8, 2026

Open

Munich, Bavaria, Germany
Hybrid
Full-time · Senior
5+ years

Apply with Referso

Fellow

GlobalFoundries · Posted Nov 9, 2026

Open

Bangalore, Karnataka, India
On-site
Full-time · Executive
20+ years

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Leads the global Hardware Engineering organization for GlobalFoundries’ MIPS Custom Silicon business, responsible for delivery of custom MCUs, MPUs and Sensor SoCs. Owns all front‑end and back‑end hardware engineering functions, including RTL Development, Design Verification, DFT, and Physical Design.

Responsibilities

Lead and scale the global hardware engineering organization covering RTL, DV, DFT, and Physical Design for custom silicon programs.
Own hardware execution strategy for MIPS‑based MCUs and radar SoCs, ensuring predictable delivery across multiple concurrent customer engagements.
Establish and enforce engineering standards, design methodologies, quality metrics, and best practices across all hardware disciplines.
Partner with Product Management and Systems Architecture to translate customer and platform requirements into executable hardware roadmaps.
Drive cross‑functional alignment with Software, Program Management, Manufacturing, Test, and Quality teams to ensure end-to-end silicon readiness.

Requirements

Bachelor’s degree in Electrical or Computer Engineering
Master’s
PhD

Skills

RTL Development Design Verification DFT

Silicon Design Validation, Senior Manager

Lattice Semiconductor · Posted Aug 31, 2026

Open

Pune, Maharashtra, India
Manager
15+ years

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As a Senior Manager in Silicon Design Validation, You lead a highly motivated team focused on ensuring the quality and performance of advanced semiconductor products, providing strategic oversight and technical direction across the full post-silicon lifecycle.

Responsibilities

Lead a highly motivated team focused on ensuring the quality and performance of advanced semiconductor products
Foster a learning environment where engineers gain hands-on experience with FPGA architectures and foundational IP blocks
Oversee the validation and characterization of analog, digital, and mixed-signal IPs
Guide the development of validation plans, including bench hardware and software requirements
Supervise the creation of custom RTL test logic to support targeted validation and characterization efforts

Requirements

Master’s degree in Electrical Engineering
Bachelor’s degree in Electrical Engineering
Nice to have: FPGA-based emulation
Nice to have: prototyping environments

Skills

Silicon validation Leadership FPGA architectures SERDES

Staff Applications Engineer

Lattice Semiconductor · Posted Jul 14, 2026

Open

Penang, Malaysia
Staff
10+ years

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Factory Applications Engineer supporting silicon design and customer enablement for low‑power programmable logic devices.

Responsibilities

Drive silicon feature enablement & improvement for a particular domain
Develop silicon enablement collaterals with focus on usability and performance
Develop and conduct trainings/workshops for sales & tech support team
Provide factory support and guidance to resolve customer issues
Collaborate closely with sales team to understand customer needs & solidify requirements to R&D

Requirements

BS/MS in Electrical Engineering

Skills

FPGA architecture PLL Embedded Memory blocks DSP blocks Input/Output blocks SSTL HSTL LVSTL

Senior ASIC/FPGA Design Engineer

RTX · Posted Nov 5, 2026

Open

McKinney, Texas, United States
On-site
Full-time · Senior
$87K–$165K per year
5+ years

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Senior ASIC/FPGA Design Engineer responsible for translating system-level requirements into FPGA, ASIC, module, and unit-level designs; developing digital architectures; and executing implementation, analysis, integration, and verification activities for advanced defense products.

Compensation

The salary range for this role is 86,800 USD - 165,200 USD.

Responsibilities

Define ASIC/FPGA requirements from system specifications
Develop digital architectures
Implement RTL designs
Perform timing, power, and functional analysis
Integrate and verify FPGA modules in a lab environment using industry-standard simulation, emulation, and hardware test tools

Requirements

Bachelor of Science in a STEM field
Nice to have: Advanced FPGA design
Nice to have: Advanced ASIC design
Nice to have: Embedded software development
Nice to have: Firmware–hardware integration

Skills

FPGA/ASIC design RTL development Verification Xilinx/Altera FPGAs High-speed interfaces (PCI/PCIe, VPX, Gb Ethernet, Interlaken)

Principal Engineer - FPGA/ASIC Design

Rolls-Royce · Posted Nov 3, 2026

Open

Remote, United States
Remote
Full-time · Principal
3+ years

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Rolls-Royce is looking for a Principal Engineer - FPGA/ASIC Design (Field Programmable Gate Arrays / Application Specific Integrated Circuit) Design Specialist to join our growing team. The role involves designing, verifying, integrating, and testing FPGA/ASIC solutions for engine control systems, traveling up to 25%.

Compensation

Pay ranges for remote employees are based on the state where the employee resides and may vary from the posted range.

Responsibilities

Participate in all phases of project, to produce detailed design documentation, verification plans and reports
The design and development of all custom digital devices (ASIC or FPGA), to support RR electronic engine control units
The verification of complex products that use FPGAs and/or ASICs to DO-254
Develop RTL utilizing a hardware description language (e.g. VHDL, Verilog, and/or SystemVerilog) and debug the design via simulation tools
Expertise achieving timing closure on FPGA designs and generating test benches

Requirements

Bachelor's degree in Electronics Engineering and/or Computer Engineering
Master's degree in Electronics Engineering and/or Computer Engineering
PhD in Electronics Engineering and/or Computer Engineering
Nice to have: oscilloscopes
Nice to have: logic analyzers

Skills

FPGA Design ASIC Design

Digital Verification Engineer (all genders)

IMS Nanofabrication GmbH · Posted Nov 3, 2026

Open

Wien, Wien, Austria
Hybrid
Full-time · Senior
€70K per year
5+ years

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In this position you will own the verification strategy, testbench development, and sign-off readiness for assigned IPs, subsystems, or distributed systems.

Compensation

attractive annual gross salary from 70.000 € (plus bonus, KV Metallgewerbe)

Responsibilities

Own the verification planning process for assigned IPs and subsystems, including definition of verification scope, strategy, coverage goals, and resource requirements
Develop and maintain reusable verification environments, testbenches, verification components, and infrastructure using industry-standard methodologies and languages
Ensure complete verification of functional requirements through directed, constrained-random, assertion-based, and coverage-driven verification
Execute verification closure activities by tracking functional, code, assertion, and other relevant coverage metrics against defined project targets
Identify, analyze, and drive resolution of design defects through systematic debug and root-cause analysis in collaboration with design engineering teams

Requirements

Bachelor's or Master's degree in Electrical Engineering, Electronics Engineering, Computer Engineering, or a related technical discipline

Skills

SystemVerilog

FPGA Engineer

FPGA Engineer

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Fellow

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Silicon Design Validation, Senior Manager

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Staff Applications Engineer

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Senior ASIC/FPGA Design Engineer

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Principal Engineer - FPGA/ASIC Design

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Digital Verification Engineer (all genders)

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RTL development jobs

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