A successful candidate will join a team designing and developing Lattice FPGA software tools at Penang. The candidate will contribute to research, design and development of FPGA Foundation IP and IP Catalog tooling.
Responsibilities
Design and implement Digital Signal Processor (DSP) DSP-centric foundation IP blocks, including multipliers, accumulators, FIR/IIR filter primitives, and arithmetic units targeted for integration into FPGA fabric
Develop RTL (VHDL/Verilog/SystemVerilog) for DSP hard macros and programmable DSP slices
Perform functional simulation and timing analysis to ensure correctness and performance targets are met
Engage with software and tools teams to ensure DSP IP is correctly modeled in simulation libraries and synthesis flows
Maintain existing software product tools and develop improvement plan to increase the test coverage to achieve high product quality
Requirements
Bachelor's or Master's degree in Electronics/Electrical Engineering, Computer Engineering, or a related discipline
Nice to have: functional verification methodologies
Nice to have: SystemVerilog Assertions
Nice to have: formal verification
Nice to have: synthesis and static timing analysis tools
Lead physical design and implementation for high-performance semiconductor IP.
Compensation
Salary commensurate with experience
Performance incentives
Equity
Responsibilities
Own RTL to GDS physical implementation flows for synthesis, floor-planning, place and route, clock tree synthesis, timing & power closure, EM/IR, PDV and final PD sign off
Own physical design & implementation of high-performance designs from block level to system level components
Deep collaboration with Micro-architects to explore performance, power and area trade-offs for high performance and low power designs
Physical implementation feasibility studies and design recommendations for best PPA
Develop methodologies and recipes for various stages of physical implementation
The applicable full salary ranges for this position, by specific state, are listed below: New York City Metro Area: $125,700.00 - $203,100.00 Non-Metro New York state & Washington state: $111,700.00 - $180,800.00
Responsibilities
Implement and optimize low-power design methodologies
Perform block- and full-chip-level power analysis and estimation using Synopsys PrimePower
Lead design of PCS/PMA RTL for high-speed interconnects in AI infrastructure.
Compensation
Salary range is $185,000 to $240,000 depending on experience, level, and business need. This role may be eligible for discretionary bonus, incentives and benefits.
Responsibilities
Design and implement PCS/PMA RTL for Ethernet, PCIe, UCIe, UALink
Develop synthesizable Verilog/SystemVerilog RTL
Implement line encoding/decoding, scrambling, alignment, FEC, PMA interface logic
Design lane-level and multi-lane logic
Translate specifications into datapaths and state machines
Requirements
Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field
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