- Hyderabad, Telangana, India
- 3+ years
RTL Design Engineer for Mixed-Signal IPs at Silicon Labs
Responsibilities
- Develop synthesizable RTL for mixed-signal IPs
- Collaborate with analog design engineers to define digital-analog interface specifications
- Ensure correct functionality and performance of mixed-signal IPs through simulation and co-verification
- Participate in design reviews and documentation
- Perform design quality checks including lint, CDC, RDC
Requirements
- B.E./B.Tech or M.S./M.Tech in Electrical Engineering, Electronics, or Computer Engineering