Lead UI modernization and architecture for Lattice EDA tools, driving migration of legacy UI codebases to modern platforms such as QT, while ensuring high performance, accessibility, and user experience excellence.
Responsibilities
Lead UI modernization initiatives
Drive migration of legacy UI codebases into newer, scalable platforms
Define future‑facing user experiences across platforms
Translate marketing requirements into UI architecture and UX flows
Own design intent throughout implementation
Requirements
BS/MS/PhD in Computer Science, Electrical Engineering, HCI, or related field
DevSecOps Engineer responsible for designing, implementing, and maintaining application delivery and load‑balancing platforms across public multi‑cloud environments.
Responsibilities
Engineer F5 BIG‑IP instances worldwide
Develop and maintain Cloud Native Load Balancer products on AWS, Alibaba Cloud, and GCP
Design and automate CDN and Public DNS solutions
Implement new solutions for Load Balancing, WAF Security, CDN, and DNS
Resolve Level 3 technical incidents
Requirements
Bachelor’s or Master’s degree in Computer Science or equivalent
Lead the DFT architecture, implementation, verification, and signoff of complex digital blocks and subsystems, driving methodology, automation, and best practices across multiple programs.
Compensation
At SiTime, we believe great work deserves great rewards. We offer a comprehensive and highly competitive compensation package designed to attract top talent. In addition to base salary, this role is eligible for a quarterly bonus tied to the achievement of innovation goals—reflecting our commitment to recognizing meaningful impact. We also offer equity grants, providing a meaningful opportunity to share in the company’s future growth and success.
Responsibilities
Serve as the technical focal point for DFT, leading architecture, implementation, verification, and signoff reviews, and establishing reusable methodologies across multiple programs.
Define DFT architecture and specifications, including scan architecture, compression, test access, clocking, test modes, core wrapping, and hierarchical DFT strategy.
Implement and validate digital DFT structures, including scan insertion, OCC insertion, advanced compression architectures such as EDT and LPCT, and core wrapping.
Develop and continuously improve automated, reproducible DFT implementation, verification, ATPG, and signoff flows to increase productivity, reduce execution risk, and ensure consistent test quality across multiple programs.
Own ATPG generation, pattern validation, fault analysis, and coverage closure, identifying and resolving testability limitations to achieve product coverage and quality targets.
Seeking a Senior Physical Design Engineer to own block-to-full-chip implementation and signoff on advanced-node, multi-die 3DIC products, driving hierarchical physical design from RTL handoff through tapeout and leading multi-physics verification.
Compensation
The anticipated base salary for this position is expected to be within the following range... $131,000—$265,000 USD
Responsibilities
Define and execute the hierarchical partitioning strategy: block boundaries, feedthroughs, pin placement, and budgeting across levels of hierarchy.
Develop and maintain floorplans, power grids, and timing/physical budgets for large multi-block SoCs.
Own the interface between block owners and top-level integration, including abstract (ILM/ETM) generation, boundary timing, and hierarchical ECO propagation.
Manage die-to-die partitioning for 3D stacks – assign logic to tiers, plan hybrid-bond / µbump / TSV interfaces, and align inter-die floorplans.
Internship focused on developing and testing EDA flows, automation tools, and infrastructure for ASIC design within Meta’s Infrastructure ASIC organization.
Responsibilities
Contribute to the development and testing of front-end or physical design implementation flows
Help build or improve internal automation tools that increase productivity across ASIC design cycles
Write and maintain scripts that support day-to-day design flow tasks
Help document EDA flows, tool behavior, and evaluation findings for the team
Partner with internal infrastructure teams on compute grid, storage, and job scheduling efficiency
Requirements
B.S. degree program in Computer Engineering, Computer Science, Electrical Engineering, or a related field
This position requires in-depth knowledge and expertise in all Physical Design aspects of taking RTL to silicon tape-out for AI/ML ecosystems and Enterprise Storage Products.
Compensation
The annual base salary range for this position is USD 121,900.00 To 195,000.00
Responsibilities
Execution of Physical Design, Synthesis, Physical Verification, and Timing Closure
Setup and Synthesizing RTL
Timing closure through various methods and strategies
Support customers by enabling and troubleshooting the digital BE design flow, running and supporting Fusion Compiler implementation flows, and providing guidance on backend implementation tools and best practices.
Responsibilities
Supporting customers by enabling and troubleshooting the digital BE design flow
Running and supporting Fusion Compiler (FC) implementation flows, including setup, execution, and analysis
Assisting customers with tool usage, flow understanding, and best practices for backend implementation
Working closely with experienced Application Engineers to learn customer environments and project requirements
Analyzing design issues and providing clear, practical guidance to resolve technical challenges
Requirements
Bachelor’s degree or higher in Electrical Engineering, Computer Science, or a related field
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