A leadership role in defining and advancing post-silicon validation strategy across products and programs, serving as a key technical resource for the Power Control team.
Responsibilities
Lead post-silicon validation strategy for complex and critical power IC programs, from pre-silicon planning through production release
Develop and advance evaluation methodologies, measurement techniques, and test frameworks that raise the standard of practice across the team
Provide technical leadership ahead of tape-out, influencing design-for-test decisions and evaluation readiness across multiple concurrent programs
Develop and champion the use of AI tools and advanced automation to accelerate design evaluation development and execution
Resolve complex characterization and silicon debug problems requiring in-depth analysis and evaluation of multiple variable factors
Provide technician level support to Production Operations and Engineering personnel, including assembly, calibration, testing, troubleshooting, and maintenance of electromechanical equipment.
Responsibilities
Assemble, calibrate, and test electromechanical equipment
Support daily production issues related to product or production equipment
Analyze and troubleshoot product and equipment failures
Monitor performance of production equipment and implement upgrades
Develop, integrate, and optimize custom test circuit architectures for NAND flash memory designs, including transistor-level digital, analog, mixed-signal, monitoring, control, and memory-array interface circuits.
Responsibilities
Interpret product specifications and test requirements; define circuit functionality, interfaces, operating limits, controllability, observability, and validation criteria.
Create, review, and optimize schematics, device sizing, bias structures, sensing and monitoring paths, multiplexers relevant to test circuits.
Analyze circuit testability and robustness to ensure compliance with quality, coverage, manufacturability, power, area, and reliability.
Validate custom test circuits using XA simulation, Verilog simulation, and mixed-signal verification environments.
Collaborate closely with layout teams on matching, parasitic sensitivity, shielding, routing, guard rings, device placement, and layout-dependent effects.
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