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1–2 jobs· newest first

Design Engineer II
Silicon Labs · Austin, US
$102K–$189KHybrid · Full-time · Mid
Staff Digital Design Engineer – SOC Low Power, Clocking & Integration
Silicon Labs · Austin, US
$151K–$280KHybrid · Full-time · Manager

+10K new in the last hour

Design Engineer II

Silicon Labs · Posted Nov 4, 2026

Austin, Texas, United States
Hybrid
Full-time · Mid
$102K–$189K per year
3–5 years

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Develop world class, highly integrated, low power System on a Chip devices for the IoT wireless market.

Compensation

The annualized base pay range for this role is expected to be between $101,500 - $188,500 USD.

Responsibilities

Develop complex SoC/chip architectures with multiple processors, digital and mixed signal subsystems, multiple power, and clock domains with a goal towards optimizing power for specific customer scenarios.
RTL design of modules through System Verilog HDL coding, adhering to quality standards.
Prepare and hold architecture, design, and verification reviews with technical staff throughout project lifecycle.
SoC level configuration and integration of digital and mixed-signal IPs.
Perform logic synthesis, full chip timing and power analysis to optimize designs for key customer scenarios.

Requirements

Master’s degree in Electrical Engineering
Nice to have: Knowledge of embedded processor systems
Nice to have: C coding
Nice to have: Experience with artificial intelligence (AI) powered tools and technologies

Skills

Verilog RTL design System Verilog HDL logic simulators design/waveform browsers power analysis tools logic synthesis timing constraints analog and mixed signal designs scripting and automation Python Perl Tcl revision control configuration management Perforce Git Methodics Verilog System Verilog

Benefits

Great medical (Choice of PPO or Consumer Driven Health Plan with HSA)
Dental and vision plans
Highly competitive salary
401k plan with match and Roth plan option
Equity rewards (RSUs)

See full job description

Staff Digital Design Engineer – SOC Low Power, Clocking & Integration

Silicon Labs · Posted Oct 29, 2026

Austin, Texas, United States
Hybrid
Full-time · Manager
$151K–$280K per year
10–20 years

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Lead the design of low‑power, highly integrated SoC devices for the IoT wireless market.

Compensation

The annualized base pay range for this role is expected to be between $150,500 - $279,500 USD.

Responsibilities

Develop complex SOC architectures with multiple processors and subsystems
Define and implement low‑power architecture and power domains
Integrate clocking infrastructure and reset architectures
Drive RTL design and integration of power management controllers
Prepare and hold architecture, design, and verification reviews

Requirements

Bachelor's in Electrical Engineering
Master's in Electrical Engineering

Skills

Verilog SystemVerilog SoC clocking architectures CDC reset domain crossing low‑power design methodologies UPF

power‑aware verification

on‑chip bus protocols

logic simulators

power analysis tools

logic synthesis

timing constraints

backend optimization

analog and mixed signal design integration

Benefits

Great medical plans
Dental and vision plans
Highly competitive salary
401k plan with match and Roth option
Equity rewards (RSUs)

See full job description