Python (pandas, NumPy, scikit‑learn, PyTorch/TensorFlow) jobs in Vietnam Skill: Python (pandas, NumPy, scikit‑learn, PyTorch/TensorFlow) Lead Engineer
Quest Global · Vietnam
Senior Engineer
Quest Global · VietnamSenior
Senior Engineer
Quest Global · VietnamSenior
PD Engineer
Quest Global · Vietnam
PD Engineer
Quest Global · Vietnam
PD Engineer
Quest Global · Vietnam
PD Engineer
Quest Global · Vietnam
Lead Engineer
Quest Global · Vietnam
30 Fresher Embedded Software Engineers (C/C++) - One Day Offer
Bosch Group · Ho Chi Minh City, Vietnam+1 more Full-time · Entry
Pentester Automation
GoTymeX · Ho Chi Minh City, VietnamHybrid · Full-time
+10K new in the last hour
Quest Global · Posted Nov 11, 2026
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Lead Engineer
Sub-system, partition, or block-level physical implementation for sub-5nm/3nm FinFET nodes. Floor-planning & Partitioning: Execute chip-top, subsystem, or macro-level floorplanning, pin placement, and power grid/PDN planning Place & Route (PnR): Drive placement, clock tree synthesis (CTS), and signal routing using advanced EDA tools – preferably Cadence Suite Timing & Power Closure (STA): Perform multi-corner multi-mode (MCMM) Static Timing Analysis, fix setup/hold violations, and run ECO (Engineering Change Order) iterations – with Critical debug and design convergence ability Power Integrity & Electromigration: Analyze and resolve IR-drop, dynamic/static power, and EM (Electromigration) issues using tools like Voltus Bachelor’s or Master’s degree in Electrical/Electronics Engineering, Computer Engineering, or VLSI/Microelectronics Quest Global · Posted Nov 11, 2026
Senior Engineer
Sub-system, partition, or block-level physical implementation for sub-5nm/3nm FinFET nodes. Floor-planning & Partitioning: Execute chip-top, subsystem, or macro-level floorplanning, pin placement, and power grid/PDN planning Place & Route (PnR): Drive placement, clock tree synthesis (CTS), and signal routing using advanced EDA tools – preferably Cadence Suite Timing & Power Closure (STA): Perform multi-corner multi-mode (MCMM) Static Timing Analysis, fix setup/hold violations, and run ECO (Engineering Change Order) iterations – with Critical debug and design convergence ability Power Integrity & Electromigration: Analyze and resolve IR-drop, dynamic/static power, and EM (Electromigration) issues using tools like Voltus Bachelor’s or Master’s degree in Electrical/Electronics Engineering Bachelor’s or Master’s degree in Computer Engineering Bachelor’s or Master’s degree in VLSI/Microelectronics Quest Global · Posted Nov 11, 2026
Senior Engineer
Sub-system, partition, or block-level physical implementation for sub-5nm/3nm FinFET nodes. Floor-planning & Partitioning: Execute chip-top, subsystem, or macro-level floorplanning, pin placement, and power grid/PDN planning Place & Route (PnR): Drive placement, clock tree synthesis (CTS), and signal routing using advanced EDA tools – preferably Cadence Suite Timing & Power Closure (STA): Perform multi-corner multi-mode (MCMM) Static Timing Analysis, fix setup/hold violations, and run ECO (Engineering Change Order) iterations – with Critical debug and design convergence ability Power Integrity & Electromigration: Analyze and resolve IR-drop, dynamic/static power, and EM (Electromigration) issues using tools like Voltus Bachelor’s or Master’s degree in Electrical/Electronics Engineering, Computer Engineering, or VLSI/Microelectronics Quest Global · Posted Nov 11, 2026
Sub-system, partition, or block-level physical implementation for sub-5nm/3nm FinFET nodes Floor-planning & Partitioning: Execute chip-top, subsystem, or macro-level floorplanning, pin placement, and power grid/PDN planning Place & Route (PnR): Drive placement, clock tree synthesis (CTS), and signal routing using advanced EDA tools – preferably Cadence Suite Timing & Power Closure (STA): Perform multi-corner multi-mode (MCMM) Static Timing Analysis, fix setup/hold violations, and run ECO iterations – with Critical debug and design convergence ability Power Integrity & Electromigration: Analyze and resolve IR-drop, dynamic/static power, and EM issues using tools like Voltus Bachelor’s or Master’s degree in Electrical/Electronics Engineering, Computer Engineering, or VLSI/Microelectronics Quest Global · Posted Nov 11, 2026
Physical Design Engineer responsible for sub-5nm/3nm FinFET node implementation, floor‑planning, placement, routing, timing, power, and verification.
Sub‑system, partition, or block‑level physical implementation for sub‑5nm/3nm FinFET nodes Floor‑planning, pin placement, and power grid/PDN planning Drive placement, clock tree synthesis, and signal routing using advanced EDA tools Perform multi‑corner multi‑mode Static Timing Analysis, fix setup/hold violations, and run ECO iterations Analyze and resolve IR‑drop, dynamic/static power, and EM issues using tools like Voltus Bachelor’s or Master’s degree in Electrical/Electronics Engineering, Computer Engineering, or VLSI/Microelectronics Quest Global · Posted Nov 11, 2026
Physical Design Engineer responsible for sub-5nm/3nm FinFET node implementation, floor‑planning, placement, routing, timing, power, and verification.
Execute chip‑top, subsystem, or macro‑level floorplanning, pin placement, and power grid/PDN planning Drive placement, clock tree synthesis, and signal routing using advanced EDA tools Perform multi‑corner multi‑mode Static Timing Analysis, fix setup/hold violations, and run ECO iterations Analyze and resolve IR‑drop, dynamic/static power, and EM issues using tools like Voltus Run and debug Design Rule Checking, Layout Versus Schematic, Antenna checks, and Electrical Rule Checking Bachelor’s or Master’s degree in Electrical/Electronics Engineering, Computer Engineering, or VLSI/Microelectronics Quest Global · Posted Nov 11, 2026
Sub-system, partition, or block-level physical implementation for sub-5nm/3nm FinFET nodes. Floor-planning & Partitioning: Execute chip-top, subsystem, or macro-level floorplanning, pin placement, and power grid/PDN planning Place & Route (PnR): Drive placement, clock tree synthesis (CTS), and signal routing using advanced EDA tools – preferably Cadence Suite Timing & Power Closure (STA): Perform multi-corner multi-mode (MCMM) Static Timing Analysis, fix setup/hold violations, and run ECO iterations – with Critical debug and design convergence ability Power Integrity & Electromigration: Analyze and resolve IR-drop, dynamic/static power, and EM issues using tools like Voltus Bachelor’s or Master’s degree in Electrical/Electronics Engineering, Computer Engineering, or VLSI/Microelectronics Quest Global · Posted Nov 11, 2026
Lead Engineer
Sub-system, partition, or block-level physical implementation for sub-5nm/3nm FinFET nodes. Floor-planning & Partitioning: Execute chip-top, subsystem, or macro-level floorplanning, pin placement, and power grid/PDN planning Place & Route (PnR): Drive placement, clock tree synthesis (CTS), and signal routing using advanced EDA tools – preferably Cadence Suite Timing & Power Closure (STA): Perform multi-corner multi-mode (MCMM) Static Timing Analysis, fix setup/hold violations, and run ECO iterations – with Critical debug and design convergence ability Power Integrity & Electromigration: Analyze and resolve IR-drop, dynamic/static power, and EM issues using tools like Voltus Bachelor’s or Master’s degree in Electrical/Electronics Engineering, Computer Engineering, or VLSI/Microelectronics Bosch Group · Posted Nov 11, 2026
Fresher Embedded Software Engineer responsible for developing, integrating, testing, and debugging embedded software for automotive applications.
Ho Chi Minh City, Ho Chi Minh City (HCMC), Vietnam Hanoi, Hanoi, Vietnam Develop, integrate, and test embedded software using C/C++ Analyze software requirements and support software design Perform software integration, testing, debugging, and issue analysis Document development and test results Work with experienced engineers and global development teams throughout the software development lifecycle Bachelor's degree in Electronics, Telecommunications, Mechatronics, Automation, Computer Engineering, Automotive Engineering or related field Nice to have: Python Nice to have: Perl Nice to have: Knowledge of sensors GoTymeX · Posted Nov 11, 2026
Penetration Tester - Automation Engineer responsible for advanced security testing, automation framework development, and vulnerability management for GoTyme banking applications.
Competitive rewards: Performance-based bonus, a pro-rated 13th-month salary, and eligibility for the Share Ownership Program participation in GoTyme Group.
Conduct advanced automated application penetration tests on web, mobile, and API applications Participate in source code reviews and testing of new security features Validate and champion secure development practices Research and recommend security standards Build tools and internal applications to discover, evaluate and mitigate security vulnerabilities Bachelor's degree in Computer Science, Computer Engineering, Information Systems, Information Security, or related field Nice to have: security certifications such as GWAPT/OSWE
13th-month salary bonus Attractive performance bonus Annual performance appraisal 100% offered salary and mandatory social insurances in 2-month probation 15++ days of annual leave
Full salary and benefits during probation meal allowance parking allowance insurance in line with Vietnamese labor law premium healthcare coverage
Lead EngineerNewQuest Global · Vietnam