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Verification Engineer Platforms Team

Codasip · Posted Nov 10, 2026

Open

Bristol, England, United Kingdom +1 more
Senior

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Verification Engineer Platforms Team

Codasip · Posted Nov 10, 2026

Open

Bristol, England, United Kingdom +1 more
Senior

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Lead Member of Technical Staff (LMTS) – Logic Design

Rambus · Posted Nov 4, 2026

Open

Hillsboro, Oregon, United States
Hybrid
8+ years

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Lead Member of Technical Staff (LMTS) – Logic Design to join the Silicon IP team in Hillsboro, Oregon, responsible for micro-architecture and RTL design of high-performance memory controllers.

Compensation

Rambus offers a competitive compensation package, including base salary, bonus, equity and employee benefits.

Responsibilities

Own micro-architecture definition and RTL design for critical blocks such as schedulers, command pipelines, coherency/ordering logic and system interfaces
Analyze performance, power, and area (PPA) trade-offs and drive design decisions based on quantitative data
Collaborate closely with verification team to shape test plans and improve verification coverage
Work with physical design team to understand and resolve timing, power, and congestion challenges
Work with verification team on regression failure debug and root cause, and provide RTL fix if necessary

Skills

System Verilog/Verilog RTL design Questa/Incisive/VCS simulator Python/Perl/TCL scripting ASIC synthesis Timing constraint

Silicon Design Verification Engineer

Advanced Micro Devices, Inc. (AMD) · Posted Sep 9, 2026

Open

Markham, Ontario, Canada

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Silicon Design Verification Engineer working with AMD SOC Verification Team to design and verify processor IP using UVM, System Verilog, C, and Python.

Responsibilities

Work with senior verification engineers and create test plans for complex IP designs
Design testbenches in System Verilog and UVM
Create and enhance constrained-random and/or directed verification environments
Formally verify designs with System Verilog Assertions and industry leading formal tools
Debug tests with design engineers

Requirements

Bachelor's or Master's degree in Computer Engineering/Electrical Engineering
Nice to have: Object oriented concepts
Nice to have: C++
Nice to have: Protocol design

Skills

System Verilog UVM C Python PCIE AMBA AXI RTL implementation

AMBA AXI jobs

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