- Pune, Maharashtra, India
- On-site
- Full-time · Staff
- 12+ years
Lattice Semiconductor is seeking a Sr. Staff Physical Design Engineer to join the HW design team focused on IP design and full chip integration.
Responsibilities
- Implementing and lead RTL to GDSII flow for complex design
- Lead one or more aspects of physical design including place & route, CTS, routing, floorplanning, powerplanning, timing and physical signoff
- Drive physical design signoff checks, including timing closure, EM/RV and physical verification (DRC, LVS)
- Drive efficiency and quality of physical design flow and methodology and work together with internal EDA team and external tool vendors
- Collaborate with RTL, DFT , verification and full chip teams to ensure robust design implementation
Requirements
- BS/MS/PhD Electronics Engineering
- Electrical Engineering
- Computer Science