Research, design, develop, and/or test electronic components and systems for semiconductor and related device manufacturing, employing knowledge of electronic theory.
Responsibilities
Verify mask designs against a host of leading edge physical and electrical checks and guidelines.
Oversee mask designs for various complex macros and tiles to integrated at the SOC level.
Utilize understanding of DRC/LVS debug, EM/IR and density concerns and contribute to all areas of design flow.
Drive projects or processes of significant technical importance.
Exercise independent judgment to select methods, techniques and evaluation criteria for obtaining results.
The full custom IC layout group is looking for a candidate to design the layout for digital and analog circuits based on schematics using industry leading CAD tools and cutting edge foundry technology.
Responsibilities
Create clean, robust layouts for digital and analog building blocks at the transistor level in Cadence Virtuoso.
Floorplan, route, and assemble lower-level cells into macros
Build black-box/abstract models and views consumed by other teams; contribute to tapeout collateral for custom blocks.
Run hierarchical checks at cell/macro levels (DRC, LVS, ERC, EM/IR, Latch-up/ESD) and iterate to closure in partnership with circuit owners.
Explore and leverage AI-assisted tools and workflows to improve layout productivity, verification efficiency, and design quality.
Requirements
Electrical Engineering Degree
Mechanical Engineering Degree
Electronics related Diploma
Nice to have: CMOS device/circuit theory
Nice to have: analog/digital layout best practices
We are looking for a Senior Mask Layout Design Engineer, someone who is excited to join a growing and dynamic group of diverse individuals responsible for handling meaningful high-speed mixed-signal circuit designs.
Responsibilities
Performing physical layout for mixed-signal functions like PLL's, high speed SerDes, Analog to Digital converters, ESD structures designs in groundbreaking sub-micron CMOS technologies using Cadence tools.
Work multi-functional with ASIC and mixed-signal engineers to customize designs for integration in VLSI products.
Take part in floor planning, custom layout and verifying against design rules and schematics.
Develop and prepare multi-dimensional layouts for semiconductor devices, leading major block developments and ensuring quality and efficiency in a globally distributed design environment.
Compensation
The US base salary range that Micron Technology estimates it could pay for this full-time position is: $70.50 - $141.00 an hour
Responsibilities
Organize and prioritize logistics and resource allocations to meet scheduled deadlines and proactively develop methodologies for issue resolution
Contribute to group management and technical innovation
Assign resources, schedule tasks, provide direction, and deliver quality-controlled results
Contribute to projects in a globally distributed design/layout environment
Effectively mentor junior team members
Requirements
AS or AS in Electronics, Electrical Engineering, or a related field plus 10 years of direct experience in semiconductor layout design
Nice to have: 15+ years direct experience in semiconductor layout design
Nice to have: BS degree in a related field
Nice to have: Project leadership in quality optimization, die size shrinkage
Nice to have: IC layout design experience with NAND, DRAM and/or SRAM
Performing physical layout for mixed-signal functions like PLL's, high speed SerDes, Analog to Digital converters, ESD structures designs in groundbreaking sub-micron CMOS technologies using Cadence tools.
Work multi-functional with ASIC and mixed-signal engineers to customize designs for integration in VLSI products.
Take part in floor planning, custom layout and verifying against design rules and schematics.
Senior Mask Layout Design Engineer responsible for high-speed mixed-signal circuit designs using sub-micron CMOS technologies.
Compensation
Your base salary will be determined based on your location, experience, and other objective job-related factors. The expected base salary ranges for this position are:
105,000 CAD – 155,000 CAD for Level 4; and 140,000 CAD – 190,000 CAD for Level 5.
Responsibilities
Performing physical layout for mixed-signal functions like PLL's, high speed SerDes, Analog to Digital converters, ESD structures designs in state-of-the-art sub-micron CMOS technologies using Cadence tools.
Work cross functionally with ASIC and mixed-signal engineers to customize designs for integration in VLSI products.
Take part in floor planning, custom layout and verifying against design rules and schematics.
As a Staff Layout Designer, you will develop and prepare multi-dimensional layouts. You will provide detailed drawings of semiconductor devices from schematics and related geometry provided by design engineers, verify data integrity, and take the lead in major block developments.
Compensation
The US base salary range that Micron Technology estimates it could pay for this full-time position is: $70.50 - $141.00 an hour. Additional compensation may include benefits, bonuses and equity.
Responsibilities
Organize and prioritize logistics and resource allocations to meet scheduled deadlines and proactively develop methodologies for issue resolution
Contribute to group management and technical innovation
Assign resources, schedule tasks, provide direction, and deliver quality-controlled results
Contribute to projects in a globally distributed design/layout environment
Perform physical layout for mixed-signal functions in sub-micron CMOS technologies using Cadence tools and collaborate with ASIC and mixed-signal engineers.
Compensation
Your base salary will be determined based on your location, experience, and other objective job-related factors. The expected base salary ranges for this position are:
105,000 CAD – 155,000 CAD for Level 4; and 140,000 CAD – 190,000 CAD for Level 5.
Responsibilities
Perform physical layout for mixed-signal functions like PLL's, high speed SerDes, Analog to Digital converters, ESD structures designs in state-of-the-art sub-micron CMOS technologies using Cadence tools.
Work cross functionally with ASIC and mixed-signal engineers to customize designs for integration in VLSI products.
Take part in floor planning, custom layout and verifying against design rules and schematics.
This role requires wide skill in the PCB industry, focusing on PCB layout and knowledge of manufacturing/assembly processes to design complex high-frequency PCBs.
Responsibilities
PCB layout and extensive knowledge of manufacturing and assembly processes and how to address problems as arise with FAB and assembly houses
Work with a wide variety of engineering disciplines to layout complex hi frequency PCB
Conduct peer and design reviews for PCB designs completed within the group as a participant
Participate in a ticket system for assigning jobs and reporting job status to the engineering community
Design dense and complex PCBs with a wide variety of component types, emphasis on RF signal requirements, and board fabrication technologies
Requirements
Associate Degree in Engineering Technology or equivalent
MTS Mask Design EngineerAdvanced Micro Devices, Inc · Santa Clara, US
Staff Layout DesignerMicron Technology · San Jose, US