The starting salary range posted for this position is $147,400.00 to $198,200.00 and reflects the projected salary range for new hires in this position in U.S. and/or Canada locations, not including incentive compensation*, equity, or benefits.
Responsibilities
Fullchip Floorplan by understanding the architecture of the design, foundry integration guidelines and IP placement constraints
Collaborate with the system and package design teams to understand the requirements and incorporate into the fullchip floorplan
Perform hierarchical implementation flow, including partition, pin assignment, clock plan and bump planning; Hands-on experience with Fullchip clock mesh and Flex-HTree methods
RTL-to-GDSII implementation: Floorplan, Power Grid plan, place and route, static timing analysis, power integrity, physical verification and equivalence checks with a focus on performance, power and die size optimization.
Analyze existing tool flows and methodologies, identifying efficiency gaps and implementing incremental or transformative enhancements.
Technical leadership for ASIC development focusing on fullchip floorplan, RTL-to-GDSII implementation, and physical design.
Compensation
The starting salary range posted for this position is $147,400.00 to $198,200.00 and reflects the projected salary range for new hires in this position in U.S. and/or Canada locations, not including incentive compensation*, equity, or benefits.
Responsibilities
Fullchip Floorplan by understanding the architecture of the design, foundry integration guidelines and IP placement constraints
Collaborate with the system and package design teams to understand the requirements and incorporate into the fullchip floorplan
Perform hierarchical implementation flow, including partition, pin assignment, clock plan and bump planning
Handson experience with Fullchip clock mesh and Flex-HTree methods
RTL-to-GDSII implementation: Floorplan, Power Grid plan, place and route, static timing analysis, power integrity, physical verification and equivalence checks
Develop chip package board PDN models and perform simulations to verify supply noise, impedance, and transient response; define PI requirements, specifications, and decoupling strategies; debug and root cause PI issues; correlate silicon measurements with simulations; collaborate with architecture, silicon, package, and board teams to deliver system aware PI solutions; improve PI methodologies, automation flows, and analysis processes.
Responsibilities
Develop chip package board PDN models and perform simulations to verify supply noise, impedance, and transient response
Define PI requirements, specifications, and decoupling strategies for all major power rails
Debug and root cause PI issues during bring up, validation, and production phases
Correlate silicon measurements with simulations and refine models accordingly
Collaborate with architecture, silicon, package, and board teams to deliver system aware PI solutions
Requirements
Bachelor's degree or foreign equivalent in Computer Engineering, Electrical Engineering, Electronic Engineering, or related field
Lead technical engagements and drive advanced design solutions for semiconductor customers as a senior Application Engineer.
Compensation
The annual salary range for California is $157,500 to $292,500. You may also be eligible to receive incentive compensation: bonus, equity, and benefits.
Responsibilities
Lead technical engagements with customers and partners to achieve best-in-class PPA
Guide adoption of Cadence’s digital implementation, signoff technologies and AgenticAI features across advanced nodes
Partner with R&D and Product Engineering to influence tool enhancements
Drive complex benchmarks, flow optimizations, and deployment of cutting-edge methodologies for Synthesis, P&R, STA, IR Drop, and power/timing closure
Represent Cadence at industry forums, author technical papers, and deliver keynote presentations
The PDK team works with internal and external foundries to develop and deploy high-quality PDKs on both mature and advanced nodes. The role involves enhancing support for business units and taking over critical activities.
Responsibilities
Install/customize foundry PDKs and provide support for various product groups.
Develop, review, update and release foundry PDK and design methodologies for various business units.
Support circuit design and layout team with PDK related tasks such as design migrations, simulation, physical verification (DRC/LVS/ERC), EMIR, and parasitic extraction (PEX/QRC/StarRC).
Provide CAD support to designers in troubleshooting project setup, design environment configuration, tool integration, and day-to-day environment issues to ensure a stable and productive design flow.
Own technically complex PDK/CAD problems from investigation through resolution.
The Engineer will lead Broadcom's design methodology for 5nm and lower technology silicon, focusing on floor-planning, placement, CTS, route, and physical verification.
Responsibilities
Understanding of SoC for top-down/bottom-up physical design integration in 5nm and lower technologies
Maintain deep functional knowledge of P&R flows
Implement timing and functional ECO
P&R, Extraction, Physical verification, work towards STA closure
Build automation flows wherever needed/adapt to existing flows for re-use
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