Diseña frameworks, servicios y soluciones potenciadas por inteligencia artificial para integrar prácticas de confiabilidad en el ciclo de desarrollo y operación, generando un impacto en la resiliencia de la plataforma y la productividad de miles de profesionales de ingeniería.
Responsibilities
Crear y evolucionar frameworks reutilizables que conviertan las mejores prácticas de SRE en soluciones simples y escalables, y mejoren las métricas de resiliencia de los sistemas
Diseñar e implementar servicios de punta a punta, desde la experiencia de usuario hasta las APIs y sus componentes técnicos, para aplicar prácticas de confiabilidad en equipos de negocio, plataforma y mobile
Desarrollar soluciones con GenAI y tecnologías agénticas para automatizar tareas de desarrollo, acelerar el diagnóstico de incidentes y generar reportes accionables, elevando la productividad sin comprometer la performance ni la calidad
Operar sistemas de gran escala y definir métricas, monitoreo y observabilidad para anticipar problemas y fortalecer la resiliencia; documentar las prácticas y diseñar experiencias de incorporación efectivas para impulsar su adopción
Internship in CPU IP Engineering focusing on RISC-V processor design and verification.
Locations (2)
Austin, Texas, United States
Santa Clara, California, United States
Compensation
$20.00 - $40.00
Responsibilities
Support RISC-V CPU microarchitecture and SystemVerilog RTL design and development
Contribute to CPU functions including instruction fetch and decode, execution, load/store, caches and memory interfaces, control and status registers, exceptions, and interrupts
Develop verification tests, assertions, checkers, and functional coverage for CPU features
Run CPU simulations and regressions and debug failures using logs, architectural traces, and waveforms
Verify processor functionality across instructions, privilege modes, memory operations, and architectural corner cases
Develop and secure application code within the IT Global Operations & Supply Chain team, focusing on product security and performance.
Compensation
Pay Range: $60/hr to $70/hr on T4
Responsibilities
Develop code, unit test, debug, and implement requests for programs, small projects, and system changes in a custom application environment with a focus on product security.
Assist in the development and documentation of system architecture, designs, and consult on encryption management solutions.
Analyze and improve performance of the infrastructure and applications.
Works with eco-system partners to help improve the security of the entire compute base from CPU to GPU.
Support global business users to ensure enterprise applications SLAs are met.
Requirements
Bachelor’s degree in Computer Science, Computer Engineering, Information Technology Systems Security or related field strongly preferred.
Design and manufacture next-generation, high-performance, power-efficient GPU micro-architectures for low power mobile devices and high-performance personal computers.
Responsibilities
Deliver high-quality, low-power graphics IP meeting performance, timing, and area goals
Explore design trade-offs while exercising rigorous design principles
Understand and contribute to pioneering micro-architectural specifications
Collaborate closely with multi-functional teams in architecture, validation, modeling, and physical design
Internship in CPU IP design and verification for RISC-V processor development
Locations (2)
Austin, Texas, United States
Santa Clara, California, United States
Compensation
$20.00 - $40.00
Responsibilities
Support RISC-V CPU microarchitecture and SystemVerilog RTL design and development
Contribute to CPU functions including instruction fetch and decode, execution, load/store, caches and memory interfaces, control and status registers, exceptions, and interrupts
Develop verification tests, assertions, checkers, and functional coverage for CPU features
Run CPU simulations and regressions and debug failures using logs, architectural traces, and waveforms
Verify processor functionality across instructions, privilege modes, memory operations, and architectural corner cases
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