Lead design verification and design engineering for subsystems in Microsoft’s cloud hardware.
Compensation
Silicon Engineering IC5 - The typical base pay range for this role across the U.S. is USD $142,800 - $274,800 per year. There is a different range applicable to specific work locations, within the San Francisco Bay area and New York City metropolitan area, and the base pay range for this role in those locations is USD $188,000 - $304,200 per year.
Responsibilities
Technically lead a subsystem as a design or DV engineer
Collaborate across teams on vertical and horizontal reuse of components
Provide technical leadership through mentorship and strong teamwork
Work effectively with Architecture, Design, DV, PD, DFT, firmware, and post-silicon teams to debug system-level issues and deliver silicon from concept through bring-up
Requirements
Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field
Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field
Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field
Nice to have: Experience debugging RTL designs
Nice to have: Experience with design quality and static checks
Lead technical verification of advanced semiconductor memory interface products, driving strategy, execution, and mentorship across projects.
Locations (2)
Raleigh, North Carolina, United States
Duluth, Georgia, United States
Responsibilities
Provide technical leadership for verification of complex semiconductor designs at the block and system level.
Define and drive verification strategies, methodologies, test plans, and coverage approaches for complex designs and features.
Lead the development and optimization of SystemVerilog/UVM verification environments and testbenches.
Drive verification execution, functional coverage, debugging, and coverage closure.
Take ownership of significant verification efforts and make independent technical decisions regarding verification methods, techniques, and priorities.
Requirements
Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field, or equivalent experience.
Lead technical verification of advanced memory interface products for data center, AI, and cloud computing applications.
Locations (2)
Melbourne, Florida, United States
Duluth, Georgia, United States
Responsibilities
Provide technical leadership for verification of complex semiconductor designs at the block and system level.
Define and drive verification strategies, methodologies, test plans, and coverage approaches for complex designs and features.
Lead the development and optimization of SystemVerilog/UVM verification environments and testbenches.
Drive verification execution, functional coverage, debugging, and coverage closure.
Take ownership of significant verification efforts and make independent technical decisions regarding verification methods, techniques, and priorities.
Requirements
Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field
Lead verification strategy and execution for complex semiconductor designs, providing technical leadership and mentorship in SystemVerilog/UVM environments.
Locations (2)
Reston, Virginia, United States
Duluth, Georgia, United States
Responsibilities
Lead verification strategy and execution for complex semiconductor designs at the block and system level
Define verification methodologies, test plans, coverage strategies, and verification environments
Architect, develop, maintain, and optimize SystemVerilog/UVM testbenches and verification environments
Drive test development, functional coverage, checkers, constrained-random verification, and coverage closure
Take technical ownership of verification for assigned blocks, features, and environments from planning through signoff
Requirements
Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field
Verify the design and implementation of cutting‑edge SerDes IPs for NVIDIA’s GPU and AI platforms.
Compensation
Your base salary will be determined based on your location, experience, and other objective job-related factors. The expected base salary ranges for this position are: 136,000 USD – 218,500 USD for Level 3; and 168,000 USD – 264,500 USD for Level 4.
Responsibilities
Develop and execute verification plans for SerDes digital designs, golden models, and microarchitecture using SystemVerilog/UVM, simulation, and hardware emulation.
Develop, bring up, and debug SerDes verification environments on Cadence Palladium, including preparing designs and testbenches for emulation and running long‑duration system scenarios.
Write and maintain C/C++ reference models, stimulus generators, checkers, and test code to support simulation and emulation.
Investigate failures across RTL, verification infrastructure, C/C++ models, and RNM models, and collaborate with designers to resolve issues.
Work with architects, digital and analog designers, and pre‑ and post‑silicon verification teams to define verification scope, close coverage, and deliver high‑quality IP on schedule.
Requirements
Bachelor’s or Master’s degree in Electrical Engineering, Computer Science, or Computer Engineering, or equivalent experience
Lead the DFT architecture, implementation, verification, and signoff of complex digital blocks and subsystems.
Compensation
In addition to base salary, this role is eligible for a quarterly bonus tied to the achievement of innovation goals—reflecting our commitment to recognizing meaningful impact. We also offer equity grants, providing a meaningful opportunity to share in the company’s future growth and success.
Responsibilities
Serve as the technical focal point for DFT, leading architecture, implementation, verification, and signoff reviews, and establishing reusable methodologies across multiple programs.
Define DFT architecture and specifications, including scan architecture, compression, test access, clocking, test modes, core wrapping, and hierarchical DFT strategy.
Implement and validate digital DFT structures, including scan insertion, OCC insertion, advanced compression architectures such as EDT and LPCT, and core wrapping.
Develop and continuously improve automated, reproducible DFT implementation, verification, ATPG, and signoff flows to increase productivity, reduce execution risk, and ensure consistent test quality across multiple programs.
Own ATPG generation, pattern validation, fault analysis, and coverage closure, identifying and resolving testability limitations to achieve product coverage and quality targets.
Requirements
MS in Electrical Engineering, Computer Engineering, or a related field
Ph.D. with a minimum of 6 years of relevant experience
