Looking for an FPGA Engineer to work on high-performance FPGA/SoC solutions with a focus on digital signal processing (DSP), algorithms, and RF applications.
Compensation
Above-market salary. Company equity package.
Responsibilities
Design and develop FPGA/SoC solutions based on Xilinx 7-Series and UltraScale/UltraScale+ devices.
Develop RTL designs using VHDL and Verilog.
Implement and optimize DSP algorithms, including FIR/IIR filters, FFT, DDC/DUC, decimation/interpolation, mixers, NCOs, and other signal-processing blocks.
Develop digital signal-processing chains for RF / SDR systems.
Work with high-speed data paths and streaming architectures.
Develop software and firmware for real-time embedded systems, implement DSP algorithms, integrate embedded systems with EW payloads, apply ML/AI algorithms, test and demonstrate work in field tests and lab demos.
Compensation
The referenced pay range is based on JHU APL’s good faith belief at the time of posting. Actual compensation may vary based on factors such as geographic location, work experience, market conditions, education/training and skill level with consideration for internal parity. For salaried employees scheduled to work less than 40 hours per week, annual salary will be prorated based on the number of hours worked. APL may offer bonuses or other forms of compensation per internal policy and/or contractual designation. Additional compensation may be provided in the form of a sign-on bonus, relocation benefits, locality allowance or discretionary payments for exceptional performance. APL provides eligible staff with a comprehensive benefits package including retirement plans, paid time off, medical, dental, vision, life insurance, short-term disability, long-term disability, flexible spending accounts, education assistance, and training and development. Minimum Rate $100,000 Annually Maximum Rate $245,000 Annually
Responsibilities
Develop software and firmware for real-time embedded systems.
Implement digital signal processing (DSP) algorithms for various types of communication, radar, and EW systems.
Integrate embedded systems with EW payloads.
Apply Machine Learning (ML) and Artificial Intelligence (AI) algorithms for EW applications.
Test and demonstrate your work in field tests and lab demos.
Requirements
Bachelor's degree in Electrical Engineering, Computer Engineering or another related technical field
Nice to have: Master's or PhD degree in Electrical Engineering or Computer Engineering
Nice to have: Experience in programming for Software Defined Radio (SDR)
Seeking an FPGA Design Engineer with strong experience developing programmable logic solutions using Xilinx Vivado, Verilog, and VHDL, targeting Xilinx Zynq UltraScale+ RFSoC, MPSoC, and Versal platforms. The role focuses on programmable logic (PL) development, RTL design, simulation, timing closure, and hardware validation.
The Senior DSP/SDR Engineer will support critical programs vital to today’s and tomorrow’s space architectures, providing strategic guidance to the US Space Force and the Intelligence Community.
Compensation
(Min - Max) $129,000.00 - $249,600.00
Responsibilities
Solve technically challenging problems in the areas of communications, signals collection, and data processing
Use technical abilities and insights to ensure ongoing development programs remain successful and to influence future missions
Apply DSP and SDR subject matter expertise to provide technical consultation and guidance to management, customers, and contractors
Independently conduct technical studies/analysis/experiments/simulations and author report findings
Leverage laboratory infrastructure, including SDR hardware platforms, FPGA development toolchains, and RF test and measurement instrumentation to develop prototypes
Requirements
Bachelor’s degree in Electrical Engineering or related technical discipline
Nice to have: Advanced degree in Electrical Engineering
Experienced Digital & DSP/ASIC R&D engineer responsible for Digital architecture and DSP algorithm development, and RTL design and verification of digital and mixed signal ASICs.
Compensation
Most offers will be between the minimum and the midpoint of the Salary Range listed below. MIN $141,750.00 - MAX $236,250.00
Responsibilities
Develop Digital architecture for digital and mixed signal ASICs
Solve complex and high impact design and development problems including customer application issues
Use product and customer applications knowledge to determine, define, develop and validate design concepts and methods
Facilitate transition of semiconductor product design and enhancements to full production/delivery
Participate in the entire spectrum of full ASIC design activities including definition, architectures, DSP design, digital logic design, IP validation, verification, and synthesis
Design, implement, and verify FPGA logic using Verilog and VHDL within the Xilinx Vivado toolchain for Zynq UltraScale+ RFSoC, MPSoC and Versal devices.
Develop programmable logic architectures for signal processing, control, and high-speed data movement applications.
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