Referso Jobs

Stage : Développement IPs de décodage IRIG (F/H)

HEMERIA · Posted Nov 9, 2026

Open

Angoulême, Nouvelle-Aquitaine, France
Internship · Intern

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Stage : Développement IPs de décodage IRIG (F/H)

HEMERIA · Posted Nov 9, 2026

Open

Angoulême, Nouvelle-Aquitaine, France
Internship · Intern

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DevOps Engineer – Embedded Systems & Test Infrastructure

Fortaegis Technologies · Posted Aug 17, 2026

Open

Amsterdam, North Holland, Netherlands

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Build and maintain the infrastructure that enables reliable integration, deployment, and testing of embedded systems on real hardware.

Responsibilities

Maintain reliable physical test environments for embedded product development and system testing.
Deploy and troubleshoot firmware, FPGA bitstreams, and software to target hardware.
Manage GitLab infrastructure and workflows supporting development and automated testing.
Automate hardware setup, deployment, and test environment management.
Improve the reproducibility, availability, and maintainability of our test infrastructure.

Requirements

Nice to have: embedded Linux
Nice to have: JTAG
Nice to have: FPGA
Nice to have: Labgrid
Nice to have: HIL

Skills

Git GitLab Linux networking scripting troubleshooting hardware test

FPGA Engineer

Fortaegis Technologies · Posted Aug 17, 2026

Open

Amsterdam, North Holland, Netherlands
5+ years

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FPGA Engineer responsible for designing and implementing FPGA solutions for networking and security products.

Responsibilities

Design and implement FPGA logic based on system-level requirements
Develop and maintain block diagrams, constraints, and pin mappings
Enable and integrate multiple interfaces (e.g., networking, memory, PCIe, high-speed SerDes)
Implement and verify FPGA functionality using VHDL/Verilog or SystemVerilog
Test, validate, and debug FPGA designs in lab and simulation environments

Skills

Xilinx FPGAs Vivado Vitis digital design timing constraints high-speed interfaces hardware/software integration testing debugging validation

EW Technique Development & Test Engineer

Johns Hopkins Applied Physics Laboratory · Posted Nov 6, 2026

Open

Lexington Park, Maryland, United States
$100K–$245K per year
5+ years

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Develop, integrate, and assess prototype EW techniques for next-generation electronic warfare systems.

Compensation

$100,000 Annually Maximum Rate $245,000 Annually

Responsibilities

Develop EW techniques, integrate prototype hardware and software capabilities, test novel concepts, and evaluate performance/effectiveness.
Design, conduct, and analyze laboratory tests and demonstrations to characterize EW technique and system performance.
Build and maintain RF budgets and conduct basic size, weight, and power (SWaP) analyses.
Communicate technical findings, test results, and recommendations to sponsors and APL staff.

Requirements

Bachelor’s degree in engineering with a concentration in signal processing, embedded software, FPGA design, RF design, or a related discipline.
Nice to have: Master’s degree or Ph.D. in electrical engineering, computer engineering, or a related discipline.
Nice to have: Ten years of experience in EW technique development, RF test and integration, or related RF systems engineering.
Nice to have: Experience with FPGA design, particularly Xilinx Vivado and Vitis.
Nice to have: Experience developing and testing EW systems.

Skills

C++

Principal FPGA Design Engineer

Advanced Micro Devices, Inc · Posted Nov 6, 2026

Open

Santa Clara, California, United States
Full-time · Senior
12+ years

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Lead FPGA system design and integration for AMD networking products

Responsibilities

Lead full design lifecycle of FPGA-based networking products
Define FPGA microarchitecture and design specifications
Develop and verify Verilog/SystemVerilog RTL
Implement FPGA flow including synthesis, place and route, timing closure
Integrate hardware, software, and diagnostic teams for rapid bring-up

Requirements

Bachelor's or Master's degree in Electrical Engineering, Electronics Engineering, Computer Engineering, or related field

Skills

FPGA design Verilog SystemVerilog Vivado Vitis Lattice toolchains PCIe I2C MDIO

Stage – Prototypage d'un radar à réseau d'antenne phasé 2D (H/F)

SAS LOOK UP SPACE · Posted Nov 6, 2026

Open

Toulouse, Occitanie, France +1 more
Hybrid
Internship · Intern

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Contribution to the development of a 2D radar (architecture + lab prototype) using transceivers and FPGAs.

Locations (2)

Toulouse, Occitanie, France
Monts-de-Randon, Occitanie, France

Compensation

Gratification : supérieure au minimum légal

Responsibilities

Réaliser un état de l’art des transceivers existants (AD9361, ADRV9002) et des FPGA (ZedBoard, Zybo, …) et choisir les dispositifs adaptés
Proposer une architecture hardware et logicielle (transceiver, FPGA, horloge externe GPSDO, splitter, combiner) pour un prototype radar 2D
Concevoir une architecture de calibration des chaînes Tx/Rx
Réaliser le montage PC, FPGA, transceiver et horloge externe
Développer la partie VHDL/FPGA pour l’émission et la réception synchronisées en temps et en phase

Requirements

Ingénieur
Master

Ingénieur conception électronique PCB/FPGA - Défense - Osny - H/F

ECM - Engineering Conception Maintenance · Posted May 26, 2026

Open

Osny, Yvelines, France
On-site
Full-time · Mid
3+ years

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Hardware design of complex systems from initial architecture to final qualification.

Responsibilities

Définir le partitionnement fonctionnel (SoC, FPGA, mémoires, I/O)
Saisie de schémas (analogique, numérique, RF)
Concevoir en RTL (VHDL/Verilog)
Implémenter des fonctions DSP (FFT, filtrage)
Analyse de timing

Requirements

Nice to have: Aéronautique
Nice to have: Défense

Skills

Conception électronique VHDL Verilog Altium Designer KiCad Eagle LTspice HyperLynx Xilinx Vivado Vitis

Sr. FPGA Engineer

QuEra Computing, Inc. · Posted Nov 6, 2026

Open

Boston, Massachusetts, United States
Senior
5+ years

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Senior FPGA Engineer to design, implement, and optimize high-performance FPGA systems for quantum computing applications.

Compensation

We consistently monitor external market data and update base salary ranges accordingly. We determine base compensation decisions on several factors, including as geographic placement, role-specific knowledge, skills, and/or experience. In addition to our base salary offerings, we also provide equity grants for all new hires.

Responsibilities

Design and implement System Verilog modules for quantum control systems
Develop and maintain Ulti-board FPGA designs (Xilinx Zynq UltraScale+ RFSoC)
Implement high-speed serial interfaces (CoaXPress, Aurora, AXI4-Stream)
Create comprehensive testbenches using System Verilog and Python (cocotb)
Develop simulation models for quantum control peripherals

Requirements

Nice to have: RF/microwave systems
Nice to have: high-speed ADC/DAC interfaces
Nice to have: image processing algorithms
Nice to have: formal verification
Nice to have: CoaXPress

Skills

FPGA development Xilinx UltraScale+ devices System Verilog high-speed serial protocols

Ingénieur Conception FPGA H/F

Expleo · Posted Nov 5, 2026

Open

Toulouse, Haute-Garonne, France
€47K–€47K per year
10+ years

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Ingénieur conception FPGA H/F

Compensation

Salaire à partir de 47 000€ suivant votre expertise

Responsibilities

Conception d’architectures FPGA
Spécifications & choix techniques
Développement & coordination
Simulation & validation virtuelle
Tests & validation hardware

Skills

VHDL Verilog FPGA Xilinx Intel NanoXplore Vivado Vitis ModelSim QuestaSim DOORS Reqtify

Post-doctorat en conception d’accélérateurs de calcul pour IA embarquée sur FPGA

Institut Mines-Télécom · Posted Nov 5, 2026

Open

Plouzané, Bretagne, France
Hybrid
Contract · Mid
€36K per year

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Postdoctoral research position focused on converting AI/DSP hybrid treatments into embedded versions on FPGA (Zynq UltraScale+) for drones and launchers.

Compensation

Rémunération indicative : 35 800€ brut annuel, selon le profil et l’expérience (charges salariales réduites en secteur public).

Responsibilities

Convert hybrid AI/DSP treatments into embeddable versions on FPGA
Integrate and optimize real-time AI/DSP hybrid architecture on FPGA Zynq UltraScale+
Account for SWaP constraints (size, weight, power) of embedded systems on drones and launchers
Validate embedded treatments (FPGA-In-the-Loop)
Implement a first complete hybrid CRPA chain

Requirements

Doctorat (obtenu depuis moins de 3 ans) en électronique numérique, systèmes embarqués ou adéquation algorithme-architecture
Nice to have: Brevitas
Nice to have: FINN
Nice to have: hls4ml

Skills

conception numérique sur FPGA VHDL Verilog HLS AMD/Xilinx tools (Vivado, Vitis)

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