As part of our fast-paced silicon group, you will become an expert in building high-speed ASICs, from specifications to final netlist for routers and switches.
Compensation
United States of America: Annual Salary USD 158,500 - 321,000 in California
Responsibilities
Produce a detailed micro-architecture specification from a functional specification of a module that meets power/area requirements
Implement the design using Verilog or System Verilog
Write functional coverage/SVA to help verification catch corner case bugs
Work with the Physical Design team for optimal floorplan and timing closure
Identify and fix timing in RTL to meet the frequency target
Verify the design and implementation of cutting‑edge SerDes IPs for NVIDIA’s GPU and AI platforms.
Compensation
Your base salary will be determined based on your location, experience, and other objective job-related factors. The expected base salary ranges for this position are: 136,000 USD – 218,500 USD for Level 3; and 168,000 USD – 264,500 USD for Level 4.
Responsibilities
Develop and execute verification plans for SerDes digital designs, golden models, and microarchitecture using SystemVerilog/UVM, simulation, and hardware emulation.
Develop, bring up, and debug SerDes verification environments on Cadence Palladium, including preparing designs and testbenches for emulation and running long‑duration system scenarios.
Write and maintain C/C++ reference models, stimulus generators, checkers, and test code to support simulation and emulation.
Investigate failures across RTL, verification infrastructure, C/C++ models, and RNM models, and collaborate with designers to resolve issues.
Work with architects, digital and analog designers, and pre‑ and post‑silicon verification teams to define verification scope, close coverage, and deliver high‑quality IP on schedule.
Requirements
Bachelor’s or Master’s degree in Electrical Engineering, Computer Science, or Computer Engineering, or equivalent experience
Be responsible for verification of the ASIC design, architecture, golden models and micro-architecture of PCIE controllers at IP/sub-system levels using state-of-the-art verification methodologies such as UVM.
Build reusable bus functional models, monitors, checkers and scoreboards following coverage driven verification methodology.
Expected to understand the design specification and implementation, define the verification scope, develop test plans, tests, and the verification infrastructure and verify the correctness of the design.
Collaborate with architects, designers, and pre and post silicon verification teams to accomplish tasks.
Verify the design and implementation of cutting‑edge SerDes IPs for NVIDIA’s high‑speed protocols.
Compensation
Your base salary will be determined based on your location, experience, and other objective job-related factors. The expected base salary ranges for this position are: 136,000 USD – 218,500 USD for Level 3; and 168,000 USD – 264,500 USD for Level 4.
Responsibilities
Develop and execute verification plans for SerDes digital designs, golden models, and microarchitecture using SystemVerilog/UVM, simulation, and hardware emulation.
Develop, bring up, and debug SerDes verification environments on Cadence Palladium, including preparing designs and testbenches for emulation and running long‑duration system scenarios.
Write and maintain C/C++ reference models, stimulus generators, checkers, and test code to support simulation and emulation.
Investigate failures across RTL, verification infrastructure, C/C++ models, and RNM models, and collaborate with designers to resolve issues.
Work with architects, digital and analog designers, and pre‑ and post‑silicon verification teams to define verification scope, close coverage, and deliver high‑quality IP on schedule.
Requirements
Bachelor’s or Master’s degree in Electrical Engineering
Bachelor’s or Master’s degree in Computer Science
Bachelor’s or Master’s degree in Computer Engineering
Serve as the primary technical resource for the verification team, leading end-to-end verification of IPs and their integration using best-in-class methodologies.
Responsibilities
Serve as the primary technical resource for the verification team, providing expert guidance.
Act as the central liaison to other verification and methodology teams at Infineon to coordinate strategies and resolve issues centrally
Lead and execute end-to-end verification of IPs and their integration using best-in-class methodologies (e.g., formal verification, AI-assisted testing)
Lead and review the third-party’s verification methodology and execution, from planning through implementation to final sign-off
Drive vendor accountability to close gaps and meet milestone targets
Requirements
Bachelor’s or master’s degree in electrical engineering, Computer Engineering, Computer Science, or a related technical field
Lead Digital Verification Engineer responsible for verification of digital RTL, development of reusable verification components and environments, flow development, test plan execution, coverage closure, and collaboration across design and verification teams.
Locations (3)
Montreal, Quebec, Canada
Ottawa, Quebec, Canada
Toronto, Quebec, Canada
Compensation
The annual salary range for MOUNT-ROYAL 01 (Montreal)is 89,600.00 - 166,400.00 CAD Annual CAD Annual. You may also be eligible to receive incentive compensation: bonus, equity, and benefits.
Responsibilities
Verify digital RTL modules
Develop reusable verification components and environments
Develop and execute test plans
Achieve functional and code coverage closure
Collaborate with design, verification, project management, and digital/analog teams
GlobalFoundries is seeking a Staff SoC Design Verification Engineer to verify custom System-on-Chip designs. The role involves independently owning verification workstreams, driving closure of objectives, solving complex technical problems, and mentoring other engineers.
Compensation
$106,000.00 - $184,000.00
Responsibilities
Review architecture and design specifications to derive verification requirements, risks, and test scenarios.
Develop and own verification plans for complex blocks, subsystems, or defined portions of larger SoC programs.
Develop and maintain reusable testbench components, tests, assertions, checkers, scoreboards, and coverage models.
Drive closure of assigned verification objectives through stimulus development, coverage analysis, and disciplined signoff tracking.
Independently analyze logs and waveforms and resolve complex, novel, or nonrecurring testbench and design failures.
Requirements
Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field
