As a CPU Core RTL Design Engineer, you will help design and optimize next-generation high-performance processor cores within AMD’s central core RTL team, which supports a wide range of products across client, server, and AI platforms.
Responsibilities
Design and implement RTL for CPU core pipeline components and related logic
Contribute to microarchitecture definition for next-generation processor cores
Collaborate with architecture, verification, and performance teams to deliver optimized designs
Analyze and improve performance, power, and timing characteristics
Support design verification, synthesis, timing closure, and physical design efforts
Leverage the understanding of the phases of silicon development to flesh out the architecture and lead development and deployment of the overall CI2 design environment as a coherent system composed of first-party and third-party tools, industry-standard and Google-specific APIs/data formats and the scalable design flows.
Collaborate with technical leaders across CI2 sites to identify opportunities for evolutionary and revolutionary tooling and methodology changes to enable convergence on a shared design environment.
Engage with other Alphabet teams, DeepMind, and Core teams to ensure CI2 stays at the forefront of advanced silicon development.
Ensure developed technologies optimize for project iteration speed while achieving the planned power, performance, cost, and quality metrics.
Partner with other members of the tools and methodologies team to apply procedural and AI-first approaches to improve efficiency.
Requirements
Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field
Nice to have: Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science
As a Digital Design Engineer, you'll join the team that designs the DSP cores and baseband hardware accelerators behind our next-generation modem products. Working alongside senior designers, you'll take on well-defined blocks and grow into the full design flow, from specification and RTL to synthesis and timing.
Responsibilities
Write and debug RTL (Verilog/SystemVerilog) for blocks within 5G baseband DSP cores and hardware accelerators, under the guidance of senior engineers.
Translate block-level specifications into clean, well-documented, synthesizable designs.
Run lint, synthesis and timing analysis on your blocks, and help resolve the issues they raise.
Support verification engineers in bringing up testbenches, debugging failures and reaching coverage goals.
Take part in design reviews and learn to weigh power, performance and area (PPA) trade-offs.
The People AI Solutions Designer is the builder. Where the People AI Deployment Lead readies HR processes for automation, the Solutions Designer takes that readied work and builds it — rapidly prototyping, coding, and shipping the agents, automations, and lightweight apps that solve real HR problems.
Compensation
Our Base Pay Range for this position
$122,100 - $162,800
Responsibilities
Translate Readied Workflows into Technical Designs
Build & Prototype Solutions
Iterate from Real Usage
Harden, Document & Hand to Operations
Maintain a Reusable Build Toolkit & Standards
Requirements
Bachelor’s degree or equivalent experience in computer science, information systems, design, engineering, or a related field
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