Lead the design and optimization of AI inference systems, integrating advanced memory and compute technologies to deliver high-performance, scalable solutions.
Compensation
Salary Range: $275,000
Responsibilities
Develop deep understanding of modern AI inference workloads and system-level behavior
Analyze execution characteristics of LLMs, generative AI, and multimodal inference
Identify bottlenecks in compute, memory, interconnect, and software
Architect software infrastructure for heterogeneous memory and compute resources
Evaluate and contribute to AI software stacks such as PyTorch, CUDA, ROCm, Triton, vLLM
Requirements
Bachelor's or Master's degree in Computer Science, Computer Engineering, Electrical Engineering, or a related technical field; PhD is a plus
Senior technical architecture role focused on designing memory and hardware architectures to solve problems related to AI workloads, focusing on performance, power, capacity, and cost.
Compensation
Salary Range: $285,000
Responsibilities
Develop system and hardware architectures for next-generation AI and inference platforms
Analyze AI workloads and translate workload characteristics into memory hierarchy, bandwidth, latency, capacity, and compute requirements
Architect solutions spanning HBM, DDR, CXL memory, memory pooling and disaggregation, memory controllers, cache hierarchy, AI accelerators, near-memory computing, processing-in-memory and storage and persistent memory
Develop architectural alternatives and conduct quantitative trade-off analysis
Define performance, power, capacity, bandwidth, latency, area, and cost targets
Lead the development of firmware that brings the high-speed peripherals of our custom AI accelerator to life.
Responsibilities
Lead a team developing low-level firmware to control, configure, and monitor PCIe, HBM, Ethernet, and other high-speed peripherals on our custom ASIC.
Own the firmware architecture and implementation for these hardware blocks, from early design through silicon bring-up and production.
Develop and validate firmware in simulation and emulation environments before silicon is available.
Work directly with ASIC architects and RTL engineers to define hardware/software interfaces, influence design decisions, and debug complex integration issues.
Bring up new peripheral blocks on first silicon, diagnose hardware and firmware issues, and drive them to resolution.
Requirements
Bachelor's degree or equivalent practical experience
Nice to have: Pre-silicon firmware development using simulation, emulation, or FPGA platforms
Nice to have: first-silicon bring-up of custom ASICs, SoCs, GPUs, or other complex chips
Nice to have: firmware development for PCIe, HBM, Ethernet, memory controllers, or high-speed interconnects
Nice to have: hardware/software co-design, including defining register interfaces and firmware requirements alongside RTL teams
Member of a group designing system-on-chip (SoC) for non-volatile memory devices, contributing to SoC and storage solution development by writing software to exercise essential SoC components.
Compensation
$35/hr - $45/hr
Responsibilities
Design system-on-chip (SoC) for non-volatile memory devices
Validate product from concept phase to mass production phase
Contribute to SoC development and storage solution development by writing software
Requirements
BS or MS in Electronic Engineering, Computer Science, or related fields
Launch your engineering career in hardware/software integration and validation of next-generation RISC-V CPUs and AI accelerators. Gain hands-on experience across hardware, software, AI workloads, and benchmarking while helping deliver high-quality Physical AI products.
Compensation
Expected Salary Range
$72,000.00 - $124,800.00
The exact Salary will be determined based on qualifications, experience and location.
Responsibilities
Execute compliance tests, regressions, benchmarks, and AI workloads across simulation, emulation, FPGA, and hardware platforms.
Reproduce, debug, document, and track failures using logs, traces, waveforms, and performance counters.
Validate CPU, NPU, memory, interrupt, exception, and software execution features with guidance from senior engineers.
Develop automation for test execution, result checking, reporting, and dashboards.
Collaborate with architecture, RTL, verification, compiler, software, performance, and infrastructure teams to resolve issues.
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