Design and run in vitro capability-verification experiments that our Foundational Research team will use to establish how in silico model performance holds up in real biology.
Compensation
Approximate compensation: $195,000 – $300,000, based on experience
Responsibilities
Design and run in vitro validations of specific capabilities that LLMs and biological AI models demonstrate computationally, on turnarounds short enough to inform pre-release decisions.
Own experimental design rigor across verification studies: power, controls, bias mitigation, replicability, and confound management.
Translate candidate verification tasks into executable experiments, including choosing proxy systems that are both informative about the capability of concern and safe to run.
Critically assess results, and put them in the context of the major threat models.
Work with the evals team to turn verification findings into in silico correlates, so that expensive wet-lab evidence becomes a cheap and repeatable measurement.
Requirements
PhD in virology, molecular biology, synthetic biology, protein design, or a closely related field
Develop and communicate data-driven and actionable insights to inform launch & go-to market strategies and meet commercial objectives within the DHH US & Global Market Engagement Team.
Locations (4)
North Wales, Pennsylvania, United States
San Francisco, California, United States
Los Angeles, California, United States
Rahway, New Jersey, United States
Compensation
The salary range for the primary location of this role is: $129,000.00 - $203,100.00
Responsibilities
Translate business needs and priorities to build analytical plans that answer business questions by providing actionable insights
Plan, build, and execute verification of new and existing features for AMD’s graphics processor IP, ensuring bug-free final design.
Responsibilities
Define and own the Emulation architecture, methodology roadmap, and platform strategy for complex SoCs
Lead the development and deployment of Emulation platforms, including RTL adaptation, implementation flows, verification infrastructure, regression environments, and system-level debug capabilities
Drive collaboration across Architecture, RTL Design, Verification, Emulation, Software, and Firmware teams to enable early hardware validation, software bring-up, and functional coverage goals
Provide technical leadership for Emulation engineers through mentoring, design reviews, best-practice development, project planning, and execution of key program milestones
Establish engineering processes, implementation methodologies, documentation standards, and continuous improvement initiatives to improve efficiency, quality, and scalability
Requirements
Bachelor's or Masters degree in computer engineering or Electrical Engineering
Engineer responsible for improving power efficiency of compute silicon through power-management feature definition, workload development, analysis, and collaboration with design teams.
Responsibilities
Define and evaluate silicon power-management features such as clock gating, power gating, idle states, and DVFS
Develop representative workloads for power measurement in simulation, emulation, and silicon
Establish power targets for IP blocks and dies and produce power rollups
Run and interpret RTL and gate-level power analysis
Partner with RTL teams to evaluate design changes for low-power states
Requirements
Bachelor’s degree in electrical engineering, computer engineering, or a related field
Develop automated methodology for chip and silicon IP design, build and integrate AI-enabled utilities, and support EDA infrastructure and design flows.
Compensation
The US hourly range for this full-time position is $25.80 to $47.80.
Responsibilities
Develop, maintain, and enhance CAD methodologies and automation flows supporting digital ASIC design, verification and implementation
Work with industry-standard EDA tools across formal verification, synthesis, static timing analysis, power analysis
Develop Python, Tcl, and shell-based scripts and utilities to automate design workflows
Explore and develop AI-assisted solutions for CAD and semiconductor design workflows
Investigate and deploy applications of large language models, retrieval-augmented generation, and AI agents for engineering automation
As a Lead (Staff) Designer, Digital, you hold a senior technical position working on our most complex digital challenges, developing innovative solutions and serving as a key technical resource and leader for the organization.
Responsibilities
Architect and design digital blocks and complex subsystems.
Write detailed block and subsystem-level specifications for design and implementation.
Use Verilog and SystemVerilog to design digital blocks, subsystems, and top level designs.
Develop block level testbenches, verify block functionality, and collaborate with verification teams to achieve full chip verification and coverage closure.
Perform block and top level linting, CDC analysis, and power analysis. Assist with synthesis, constraints, pnr and timing closure.
Requirements
MSEE
PhD in Electrical Engineering
Nice to have: high-speed SerDes transceiver architectures
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