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Develop and support automated block and full chip level signoff flows, enable hierarchical timing flows, perform power optimizations, generate block level budgets, drive custom IP integration and timing checks, and collaborate with design, DFT, architecture and power teams.
As an ASIC STA Engineer, you will have responsibilities spanning all aspects of SoC design in terms of timing. Key responsibilities include timing sign-off, STA and sign-off flow development, ownership of Full chip, IP, and block level timing constraints both for regular and custom timing requirements from synthesis to sign-off to achieve sign-off quality timing constraints.
Physical Design Engineer
Physical Design Engineer