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On-site · Full-time · Mid
On-site
Full-time · Senior
Principal
$158K–$293KOn-site · Full-time · Senior
+10K new in the last hour
Develop/support automated block and full chip level signoff flows, Full Chip Timing/Noise convergence and full signoff for high quality TO, Enable hierarchical Timing flows, Power optimizations, Generate block level budget and context for correlation with Full Chip, Drive custom IP integration and custom timing checks flows, Close work with Design, DFT, architecture and Power team.
Develop and support automated block and full chip level signoff flows, enable hierarchical timing flows, perform power optimizations, generate block level budgets, drive custom IP integration and timing checks, and collaborate with design, DFT, architecture and power teams.
Performs physical design implementation of custom IP and SoC designs from RTL to GDS to create a design database that is ready for manufacturing.
Senior technical authority for complex custom SoC designs, defining DFT strategy and architecture, leading high-impact initiatives, and influencing cross-functional technical direction.
The Architect will serve as a technical leader within Cadence’s North America Field Applications Team, driving strategic customer engagements and influencing next-generation EDA & Agentic-AI solutions.
The annual salary range for California is $157,500 to $292,500. You may also be eligible to receive incentive compensation: bonus, equity, and benefits.