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On-site · Full-time · Staff
$158K–$293K
$174K–$225KOn-site · Full-time · Associate
+10K new in the last hour
Lattice Semiconductor is seeking a Sr. Staff Physical Design Engineer to join the HW design team focused on IP design and full chip integration.
Lead technical engagements and drive strategic customer engagements within Cadence’s North America Field Applications Team.
The annual salary range for California is $157,500 to $292,500. You may also be eligible to receive incentive compensation: bonus, equity, and benefits.
Physical Design Engineer works with the logic design team to drive physical aspects, complete netlist to GDS2 implementation, and manage timing timing, physical, and electrical verification for SoC partitions.
The base pay range for this role is between $174,149 - $225,300/yr