Lead a globally distributed engineering organization spanning design, verification, physical design, DFT, and silicon validation across multiple sites to deliver advanced connectivity silicon products.
Own the bringup and New Product Introduction (NPI) phases to enable custom silicon products, validating ASIC subsystems such as boot, PCIe, memory (e.g., HBM, SRAM), compute cores, and power.
Own the bringup and New Product Introduction (NPI) phases to enable custom silicon products, validating ASIC subsystems such as boot, PCIe, memory (e.g., HBM, SRAM), compute cores, and power.
Design, develop, operate, and maintain detailed validation tests and test plans in coordination with cross-functional architecture, design, and software teams.
Perform system characterization, qualification, and debugging to root-cause failures across both pre-silicon prototyping platforms and post-silicon production.
Provide feedback to improve critical features like power management quality, performance, and reliability through successive generations of designs.
Partner with customers, systems, manufacturing, diagnostics, and vendor teams to resolve issues and eliminate failures by "shifting left" in the production and deployment lifecycle.
Requirements
Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
Nice to have: Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field.
Own end-to-end talent acquisition for Lattice Semiconductor's engineering organization, focusing on niche FPGA/semiconductor talent across India and global markets.
Responsibilities
Own end-to-end recruiting from sourcing through offer close for niche FPGA/semiconductor talent
Build and execute proactive deep sourcing strategies using Boolean search, headhunting, and AI/ML recruiting tools
Source passive candidates through unconventional channels such as industry hackathons, technical communities, open-source contributors, and referral networks
Partner with local India hiring managers to build full end-to-end recruiting ownership, then expand scope to support US-based sourcing needs
Track hiring metrics and provide data-driven insights on market dynamics, talent availability, and competitive hiring trends
Requirements
Master's degree in HR, Business, or Engineering-related field; talent acquisition or recruiting certification
Nice to have: North America talent market
Nice to have: APAC talent market
Nice to have: India talent market
Nice to have: startup or high-growth product company experience
Seeking an expert and innovative Director of NAND Design for Test (DFT) to lead the global DFT strategy, architecture, and execution for advanced NAND Flash products at Micron Semiconductor Italia.
Responsibilities
Define and lead the global NAND DFT vision, strategy, and technical roadmap across product programs and technology generations.
Own DFT architecture, methodology, integration, verification, coverage closure, and design sign-off from early product definition through tape-out.
Partner with Design and Project teams to embed testability early and resolve performance, power, area, reliability, cost, and schedule trade-offs.
Drive reusable methodologies, automation, and DFT and design-for-debug innovation.
Build, develop, and inspire a high-performing global DFT organization.
Lead complex ASIC/SoC development programs from concept through silicon production and product release.
Responsibilities
Lead end-to-end ASIC/SoC development programs
Develop, maintain, and manage integrated program plans, schedules, milestones, dependencies, and critical paths
Coordinate closely with architecture, digital design, analog design, verification, physical design, DFT, CAD, product engineering, packaging, foundry, and operations teams
Drive program reviews, monitor progress, identify risks, and implement mitigation plans
Establish clear ownership, accountability, governance, and escalation processes
Requirements
Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical discipline
Nice to have: Master's degree in Engineering, Computer Science, or Business Administration
Nice to have: PMP certification
Nice to have: advanced technology nodes (3nm, 2nm, and beyond)
Expected Base Pay Range (USD) 242,080 - 362,600, $ per annum
Responsibilities
Lead a globally distributed engineering organization spanning design, verification, physical design, DFT, and silicon validation across sites including Irvine, Santa Clara, Ottawa, Pavia, Aachen, Bucharest, Vietnam, and India
Own end-to-end execution of one or more major product families — from RTL design through tape-out, bringup, and production release
Drive first-silicon success across next-generation 200G/lane and beyond connectivity products on 3nm and 2nm process nodes
Establish and continuously improve design flows, verification methodologies, DFT strategies, and emulation infrastructure to accelerate delivery and quality
Partner with architecture, systems, and product management teams to define the technical roadmap for next-generation connectivity products
Requirements
BS/MS/PhD in Electrical Engineering, Computer Engineering, or related field
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