Synopsys Primetime jobs

Physical Design and Verification Engineer

Neuralink · Posted Nov 5, 2026

Open

South San Francisco, California, United States
Full-time · Senior
$131K–$265K per year
5+ years

Physical Design and Verification Engineer

Neuralink · Posted Nov 5, 2026

Open

South San Francisco, California, United States
Full-time · Senior
$131K–$265K per year
5+ years

Physical Design Engineer

Apple · Posted Nov 5, 2026

Open

Cupertino, California, United States +1 more
On-site
Full-time · Associate
$174K–$225K per year
2+ years

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Physical Design Engineer works with the logic design team to drive physical aspects, complete netlist to GDS2 implementation, and manage timing timing, physical, and electrical verification for SoC partitions.

Locations (2)

Cupertino, California, United States
United States

Compensation

The base pay range for this role is between $174,149 - $225,300/yr

Responsibilities

Work with logic design team to understand partition architecture and drive physical aspects early in design cycle
Complete netlist to GDS2 implementation for partition(s) meet schedule and design goals
Be responsible for timing, physical & electrical verification, driving the signoff closure for the partitions
Resolve design and flow issues related to physical design, identifying potential solutions and driving execution
Be a focal point for place and route, driving the work among place and route engineers, setting goals and milestones, planning short and long-term work

CPU Implementation Engineer

Apple · Posted Nov 5, 2026

Open

Cupertino, California, United States +1 more
On-site
Full-time
$174K–$225K per year

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Work on block and full-chip EM/IR and electrical verification, power grid construction, and implementation tasks for Apple’s chip designs.

Locations (2)

Cupertino, California, United States
United States

Compensation

base pay range for this role is between $174,149 - $225,300/yr

Responsibilities

Work on block and full-chip EM/IR and electrical verification
Work on power grid and methodologies and implementation
Script using Perl/Python to automate tasks and improve debug efficiency
Work with implementation/CAD team during full design cycle to drive analysis fixes/signoff closure for takeout
Analysis and comparison of various tool methodologies to determine the best suited for Power grid construction

Requirements

Master’s degree or foreign equivalent in Electrical and Computer Engineering, Electrical Engineering, Electronics Engineering, or a related field

Principal PCS/PMA RTL Design Engineer

Astera Labs · Posted Nov 3, 2026

Open

San Jose, California, United States
On-site
Full-time · Manager
$185K–$240K per year
3+ years

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Lead design of PCS/PMA RTL for high-speed interconnects in AI infrastructure.

Compensation

Salary range is $185,000 to $240,000 depending on experience, level, and business need. This role may be eligible for discretionary bonus, incentives and benefits.

Responsibilities

Design and implement PCS/PMA RTL for Ethernet, PCIe, UCIe, UALink
Develop synthesizable Verilog/SystemVerilog RTL
Implement line encoding/decoding, scrambling, alignment, FEC, PMA interface logic
Design lane-level and multi-lane logic
Translate specifications into datapaths and state machines

Requirements

Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field
Nice to have: Master's degree
Nice to have: PAM4 signaling
Nice to have: FEC
Nice to have: PIPE specification

Skills

Verilog SystemVerilog High-speed serial protocols PCS/PMA logic RTL design

Physical Design and Verification Engineer

Physical Design and Verification Engineer

Compensation

Responsibilities

Requirements

Skills

Benefits

Physical Design Engineer

Locations (2)

Compensation

Responsibilities

CPU Implementation Engineer

Locations (2)

Compensation

Responsibilities

Requirements

Principal PCS/PMA RTL Design Engineer

Compensation

Responsibilities

Requirements

Skills

Requirements

Skills

Benefits

Skills

Benefits