Seeking an RTL Design Engineer to join the Neural Network Engine (NNE) design team to define microarchitecture and deliver production-quality RTL for compute, memory, datapath, and control blocks in an advanced SoC environment.
Compensation
The listed base salary range for this role is $237,000 - $296,000 for San Francisco Area based applicants.
Digital Design Engineer to develop ASIC for next-generation AI computing architecture.
Compensation
$123,000—$175,000 USD
Responsibilities
Develop RTL (SystemVerilog) modules with DFT considerations for IC development
Debug complex logic and mixed signal simulations
Understand and integrate silicon photonic communication and compute technology into digital accelerator design
Actively work with Architecture, Design Verification, Physical Design, Photonic, Analog and Software teams to realize high performance, low power designs in advanced technology nodes
Create design specifications and documentation to facilitate collaboration with partner teams
Requirements
Bachelor’s degree in Electrical or Computer Engineering (or related fields)
Nice to have: Master's degree in Electrical or Computer Engineering
Develop RTL (SystemVerilog) modules for ASIC design, debug complex logic and mixed-signal simulations, integrate silicon photonic communication into digital accelerator design, and collaborate across architecture, verification, physical design, photonic, analog, and software teams.
Compensation
$154,000—$218,000 USD
Responsibilities
Develop RTL modules with DFT considerations for IC development
Debug complex logic and mixed signal simulations
Integrate silicon photonic communication and compute technology into digital accelerator design
Collaborate with Architecture, Design Verification, Physical Design, Photonic, Analog and Software teams
Create design specifications and documentation
Requirements
Bachelor’s degree in Electrical or Computer Engineering (or related fields)
Nice to have: Master's degree in Electrical or Computer Engineering
Lead the development of ASICs for next-generation AI computing architecture, designing RTL modules, debugging mixed-signal simulations, and integrating silicon photonic communication into digital accelerator designs.
Compensation
$164,000—$222,000 USD
Responsibilities
Develop RTL (SystemVerilog) modules with DFT considerations for IC development
Debug complex logic and mixed signal simulations
Integrate silicon photonic communication and compute technology into digital accelerator design
Collaborate with Architecture, Design Verification, Physical Design, Photonic, Analog and Software teams to realize high performance, low power designs
Create design specifications and documentation
Requirements
Bachelor’s degree in Electrical or Computer Engineering (or related fields)
Nice to have: Master's degree in Electrical or Computer Engineering
Develop and refine DFx flows and methodology that integrate cleanly with front‑end and physical design flows, balancing coverage, test cost, and design intrusiveness.
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