The starting salary range posted for this position is $186,900.00 to $267,700.00 and reflects the projected salary range for new hires in this position in U.S. and/or Canada locations, not including incentive compensation*, equity, or benefits.
Responsibilities
Lead the architecture and design of complex CPU subsystems for next‑generation high‑performance networking switch ASICs
Use expertise in all stages of ASIC development from specification and RTL design through post‑silicon bring‑up
Collaborate closely with SDK, board‑support package (BSP), and Network OS (NOS) software teams to define driver interfaces, register maps, and memory consistency models
Support early emulation and FPGA platforms
Requirements
Bachelor's degree
Master's degree
PhD
Nice to have: Leading CPU/SoC subsystem architecture
Work with teams on floor-planning, timing constraints, physical synthesis, formal verification, clock tree optimization, routing, extraction, timing closure, DFT, signal integrity, physical verification and DFM.
Collaborate on executing the block level place and route assignments from Netlist through GDS flow.
Interact with design team with purpose to solve problems and propose physical design engineering ideas.
Coordinate all timing budgeting required for physical design task with respective teams.
Close STA timing across all corners and modes for blocks and should be able to generate ECO independently.
Work with teams on floor-planning, timing constraints, physical synthesis, formal verification, clock tree optimization, routing, extraction, timing closure, DFT, signal integrity, physical verification and DFM
Collaborate on executing the block level place and route assignments from Netlist through GDS flow
Interact with design team to solve problems and propose physical design engineering ideas
Coordinate all timing budgeting required for physical design task with respective teams
Close STA timing across all corners and modes for blocks and generate ECO independently
Sr. Engineer - ASIC PD responsible for physical design tasks including floor-planning, timing closure, and block level place and route.
Responsibilities
Working with teams on floor-planning, timing constraints, physical synthesis, formal verification, clock tree optimization, routing, extraction, timing closure, DFT, signal integrity, physical verification and DFM
Engineer will be responsible for working with teams on floor-planning, timing constraints, physical synthesis, formal verification, clock tree optimization, routing, extraction, timing closure, DFT, signal integrity, physical verification and DFM
Engineer will be responsible for working with teams on executing the block level place and route assignments from Netlist through GDS flow
Interacting with design team with purpose to solve problems and propose physical design engineering ideas
To Coordinate all timing budgeting required for physical design task with respective teams
To close STA timing across all corners and modes for blocks and should be able to generate ECO independently
Engineer will be responsible for working with teams on floor-planning, timing constraints, physical synthesis, formal verification, clock tree optimization, routing, extraction, timing closure, DFT, signal integrity, physical verification and DFM
Engineer will be responsible for working with teams on executing the block level place and route assignments from Netlist through GDS flow
Interacting with design team with purpose to solve problems and propose physical design engineering ideas
To Coordinate all timing budgeting required for physical design task with respective teams
To close STA timing across all corners and modes for blocks and should be able to generate ECO independently
Engineer will be responsible for working with teams on floor-planning, timing constraints, physical synthesis, formal verification, clock tree optimization, routing, extraction, timing closure, DFT, signal integrity, physical verification and DFM
Engineer will be responsible for working with teams on executing the block level place and route assignments from Netlist through GDS flow
Interacting with design team with purpose to solve problems and propose physical design engineering ideas
To Coordinate all timing budgeting required for physical design task with respective teams
To close STA timing across all corners and modes for blocks and should be able to generate ECO independently
Develop world class, highly integrated, low power System on a Chip devices to serve the IoT wireless market.
Compensation
The annualized base pay range for this role is expected to be between $101,500 - $188,500 USD. Actual base pay could vary based on factors including but not limited to experience, geographic location where work will be performed and applicant’s skill set. The base pay is just one component of the total compensation package for employees. Other rewards may include an annual cash bonus, equity package and a comprehensive benefits package.
Responsibilities
Develop complex SoC/chip Architectures with multiple processors, digital and mixed signal subsystems, multiple power, and clock domains with a goal towards optimizing power for specific customer scenarios.
RTL design of modules through SystemVerilog HDL coding, adhering to quality standards.
Prepare and hold architecture, design, and verification reviews with technical staff throughout project lifecycle.
SoC level configuration and integration of digital and mixed-signal IPs.
Perform logic synthesis, full chip timing and power analysis to optimize designs for key customer scenarios.
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