Define DFT strategy, architecture, methodology, and signoff criteria for complex SoCs and multiple interdependent technical areas.
Lead high-impact DFT initiatives spanning planning, risk management, execution, manufacturing readiness, silicon quality, and test cost.
Architect scalable solutions for scan and ATPG, compression, memory test and repair, logic BIST, test access, boundary scan, IJTAG, and mixed-signal test.
Establish readiness and signoff frameworks, close critical risks, and provide evidence-based recommendations to engineering and program leadership.
Solve critical DFT problems of exceptional complexity and establish reusable approaches across products and teams.
Requirements
Master’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field
Bachelor’s degree with 15+ years of relevant experience
Lead and architect DFT/Test methodology for complex mixed-signal SOCs across multiple generations, mentoring a team of DFT engineers and driving new methodologies.
Compensation
Expected Base Pay Range (USD) 182,360 - 273,200, $ per annum
Responsibilities
Architect and lead DFT/Test methodology
Implement DFT/DFX features
Validate and debug designs
Mentor and guide DFT engineers
Define and enhance DFT methodologies and tools
Requirements
Bachelor’s degree in Computer Science, Electrical Engineering or related fields
Master’s degree and/or PhD in Computer Science, Electrical Engineering or related fields
DFT Engineering Director, CPU Cores Design for TestabilityAdvanced Micro Devices, Inc · Austin, US+4 more