Computer experience using word processing and data entry software jobs in Vietnam Skill: computer experience using word processing and data entry software Internship_Translation-Requirement Management Support (Japanese + English required)
Bosch Group · Thành phố Hồ Chí Minh, VietnamInternship · Intern
Sales Director
Super Micro Computer · Ho Chi Minh City, Vietnam
Project Coordinator
Alstom · Hanoi, Vietnam
Lead Engineer
Quest Global · Vietnam
Senior Engineer
Quest Global · VietnamSenior
Senior Engineer
Quest Global · VietnamSenior
PD Engineer
Quest Global · Vietnam
PD Engineer
Quest Global · Vietnam
PD Engineer
Quest Global · Vietnam
PD Engineer
Quest Global · Vietnam
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Bosch Group · Posted Nov 11, 2026
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Support translation and requirement management for technical documents in Japanese and English.
Receive specification documents from customer. Import the content of specification in various formats (word, excel, pdf, matrix...) into Doors system, manage version, set attribute and layout as per customer requirement. Ensure consistency of attribute, layouts for all modules. Reflect changes of specification into system when having updates. Develop and manage project metrics. Bachelor's degree in Linguistics Bachelor's degree in Business Administration Monthly Internship allowance Meal & Parking allowance 1 day of paid leave per month Good benefits of company activities such as: football, badminton, yoga, Aerobic, team building Super Micro Computer · Posted Nov 11, 2026
Sales Director responsible for maintaining the quality, efficiency, and integrity of Supermicro's sales process through various means of marketing activities and working with cross functional teams, including Engineering, Finance, Logistics, and Programs.
Search for and develop new accounts; some travel required. Approach customers in Government, IoT ,Telco, Data centers/Cloud, Gaming, and HPC Initiate outbound cold calls or emails to potential customers, direct and indirect, e.g. System Integrators, VARs, OEMs and Enterprise end users Successfully manage and overcome objections Qualify opportunities, create target lists for vertical markets Bachelor degree in Technology, Engineering or similar fields Alstom · Posted Nov 11, 2026
Coordinate and execute railway/rolling‑stock projects, ensuring schedule, deliverables, costs, documentation and stakeholder communication.
Implement and adhere to Project Management Processes Serve as primary contact to the PMO Office Manage customer and stakeholder communication Coordinate monthly reporting Track deliverables and external submission progress Master Degree in any Engineering discipline Bachelor Degree in any Engineering discipline Quest Global · Posted Nov 11, 2026
Lead Engineer
Sub-system, partition, or block-level physical implementation for sub-5nm/3nm FinFET nodes. Floor-planning & Partitioning: Execute chip-top, subsystem, or macro-level floorplanning, pin placement, and power grid/PDN planning Place & Route (PnR): Drive placement, clock tree synthesis (CTS), and signal routing using advanced EDA tools – preferably Cadence Suite Timing & Power Closure (STA): Perform multi-corner multi-mode (MCMM) Static Timing Analysis, fix setup/hold violations, and run ECO (Engineering Change Order) iterations – with Critical debug and design convergence ability Power Integrity & Electromigration: Analyze and resolve IR-drop, dynamic/static power, and EM (Electromigration) issues using tools like Voltus Bachelor’s or Master’s degree in Electrical/Electronics Engineering, Computer Engineering, or VLSI/Microelectronics Quest Global · Posted Nov 11, 2026
Senior Engineer
Sub-system, partition, or block-level physical implementation for sub-5nm/3nm FinFET nodes. Floor-planning & Partitioning: Execute chip-top, subsystem, or macro-level floorplanning, pin placement, and power grid/PDN planning Place & Route (PnR): Drive placement, clock tree synthesis (CTS), and signal routing using advanced EDA tools – preferably Cadence Suite Timing & Power Closure (STA): Perform multi-corner multi-mode (MCMM) Static Timing Analysis, fix setup/hold violations, and run ECO (Engineering Change Order) iterations – with Critical debug and design convergence ability Power Integrity & Electromigration: Analyze and resolve IR-drop, dynamic/static power, and EM (Electromigration) issues using tools like Voltus Bachelor’s or Master’s degree in Electrical/Electronics Engineering Bachelor’s or Master’s degree in Computer Engineering Bachelor’s or Master’s degree in VLSI/Microelectronics Quest Global · Posted Nov 11, 2026
Senior Engineer
Sub-system, partition, or block-level physical implementation for sub-5nm/3nm FinFET nodes. Floor-planning & Partitioning: Execute chip-top, subsystem, or macro-level floorplanning, pin placement, and power grid/PDN planning Place & Route (PnR): Drive placement, clock tree synthesis (CTS), and signal routing using advanced EDA tools – preferably Cadence Suite Timing & Power Closure (STA): Perform multi-corner multi-mode (MCMM) Static Timing Analysis, fix setup/hold violations, and run ECO (Engineering Change Order) iterations – with Critical debug and design convergence ability Power Integrity & Electromigration: Analyze and resolve IR-drop, dynamic/static power, and EM (Electromigration) issues using tools like Voltus Bachelor’s or Master’s degree in Electrical/Electronics Engineering, Computer Engineering, or VLSI/Microelectronics Quest Global · Posted Nov 11, 2026
Sub-system, partition, or block-level physical implementation for sub-5nm/3nm FinFET nodes Floor-planning & Partitioning: Execute chip-top, subsystem, or macro-level floorplanning, pin placement, and power grid/PDN planning Place & Route (PnR): Drive placement, clock tree synthesis (CTS), and signal routing using advanced EDA tools – preferably Cadence Suite Timing & Power Closure (STA): Perform multi-corner multi-mode (MCMM) Static Timing Analysis, fix setup/hold violations, and run ECO iterations – with Critical debug and design convergence ability Power Integrity & Electromigration: Analyze and resolve IR-drop, dynamic/static power, and EM issues using tools like Voltus Bachelor’s or Master’s degree in Electrical/Electronics Engineering, Computer Engineering, or VLSI/Microelectronics Quest Global · Posted Nov 11, 2026
Physical Design Engineer responsible for sub-5nm/3nm FinFET node implementation, floor‑planning, placement, routing, timing, power, and verification.
Sub‑system, partition, or block‑level physical implementation for sub‑5nm/3nm FinFET nodes Floor‑planning, pin placement, and power grid/PDN planning Drive placement, clock tree synthesis, and signal routing using advanced EDA tools Perform multi‑corner multi‑mode Static Timing Analysis, fix setup/hold violations, and run ECO iterations Analyze and resolve IR‑drop, dynamic/static power, and EM issues using tools like Voltus Bachelor’s or Master’s degree in Electrical/Electronics Engineering, Computer Engineering, or VLSI/Microelectronics Quest Global · Posted Nov 11, 2026
Physical Design Engineer responsible for sub-5nm/3nm FinFET node implementation, floor‑planning, placement, routing, timing, power, and verification.
Execute chip‑top, subsystem, or macro‑level floorplanning, pin placement, and power grid/PDN planning Drive placement, clock tree synthesis, and signal routing using advanced EDA tools Perform multi‑corner multi‑mode Static Timing Analysis, fix setup/hold violations, and run ECO iterations Analyze and resolve IR‑drop, dynamic/static power, and EM issues using tools like Voltus Run and debug Design Rule Checking, Layout Versus Schematic, Antenna checks, and Electrical Rule Checking Bachelor’s or Master’s degree in Electrical/Electronics Engineering, Computer Engineering, or VLSI/Microelectronics Quest Global · Posted Nov 11, 2026
Sub-system, partition, or block-level physical implementation for sub-5nm/3nm FinFET nodes. Floor-planning & Partitioning: Execute chip-top, subsystem, or macro-level floorplanning, pin placement, and power grid/PDN planning Place & Route (PnR): Drive placement, clock tree synthesis (CTS), and signal routing using advanced EDA tools – preferably Cadence Suite Timing & Power Closure (STA): Perform multi-corner multi-mode (MCMM) Static Timing Analysis, fix setup/hold violations, and run ECO iterations – with Critical debug and design convergence ability Power Integrity & Electromigration: Analyze and resolve IR-drop, dynamic/static power, and EM issues using tools like Voltus Bachelor’s or Master’s degree in Electrical/Electronics Engineering, Computer Engineering, or VLSI/Microelectronics
Sales DirectorNewSuper Micro Computer · Ho Chi Minh City, Vietnam
Project CoordinatorNewAlstom · Hanoi, Vietnam
Lead EngineerNewQuest Global · Vietnam