We are seeking an experienced ASIC Emulation and Verification Engineer to bridge the gap between simulation and hardware acceleration.
Compensation
The annual base salary range for this position is USD 121,900.00 To USD 195,000.00
Responsibilities
Compile, synthesize, and map complex RTL databases onto Cadence Palladium hardware acceleration systems
Resolve compilation errors, manage clocking/memory overrides, and successfully bring up full-chip and sub-system emulation models
Partner closely with firmware engineering teams to accelerate early FW bring-up on the Palladium platform
Provide hardware models, map memory spaces, and configure virtual debuggers to allow teams to boot low-level bootloaders, drivers, and operating systems
Perform traditional pre-silicon verification tasks using SystemVerilog and UVM
Requirements
Bachelor’s Degree in Electrical Engineering, Computer Engineering, or a related field
Lead verification engineering for custom silicon at Annapurna Labs, ensuring high-speed I/O and system-wide integrity across SoC components.
Compensation
The base salary range for this position is listed below. Your Amazon package will include sign-on payments and restricted stock units (RSUs). Final compensation will be determined based on factors including experience, qualifications, and location. Amazon also offers comprehensive benefits including health insurance (medical, dental, vision, prescription, Basic Life & AD&D insurance and option for Supplemental life plans, EAP, Mental Health Support, Medical Advice Line, Flexible Spending Accounts, Adoption and Surrogacy Reimbursement coverage), 401(k) matching, paid time off, and parental leave. Learn more about our benefits at https://amazon.jobs/en/benefits.
USA, CA, Cupertino - 277,400.00 - 350,000.00 USD annually
Responsibilities
Architect and implement end-to-end verification strategies addressing system-wide implications and cross-module interactions
Drive unified verification plans across multiple environments, tools and methodologies
Provide technical leadership for verification efforts, guiding architectural decisions and methodology choices
Own the technical direction and drive resolution of complex verification challenges at sub-system and chip-level, providing hands‑on technical guidance and effective solutions
Guide and mentor team members on best practices, methodology improvements, and technical problem‑solving
Requirements
Bachelor's degree in Electrical Engineering or a related field
Nice to have: verifying at multiple levels of logic from IP blocks to SoCs to full system testing
Design Engineering Architect – Systems and Interfaces
Lead technical architecture for Cadence interface IP integration in customer SoCs, driving pre‑ and post‑sales engagements and product definition.
Compensation
The annual salary range for California is $185,500 to $344,500. You may also be eligible to receive incentive compensation: bonus, equity, and benefits.
Responsibilities
Serve as the technical authority for Cadence interface controllers and system‑level IP integration in customer engagements.
Lead resolution of critical customer issues and escalations, coordinating with development engineering, sales, marketing, and customer support teams on pre‑sales and post‑sales engagements.
Develop reference designs, technical collateral, and application notes for IP integration, SoC design, and verification.
Develop and deliver training for customers and field application engineers.
Provide advanced technical guidance to customers, support teams, and field application engineers on IP integration, configuration, and system‑level deployment.
Requirements
Bachelor's in Electrical Engineering or Computer Science
Master's in Electrical Engineering or Computer Science
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