Support the development and delivery of advanced communication solutions in aerospace and defense as a Systems Engineering I within Strategic Defense Solutions.
Compensation
The salary range for this role is 57,200 USD - 108,800 USD.
Responsibilities
Collaborate with experienced engineers to solve complex problems
Participate in evaluation of features, design efforts, trade studies, integration, testing, and verification planning
Create, decompose, and trace requirements for communications systems on military platforms
Work with a model-based systems engineering application to create logical and physical design diagrams
Participate in hands‑on lab efforts from setup to validation
Requirements
Bachelor’s degree in Electrical Engineering, Computer Engineering or related STEM
Lead the development, validation, and support of hardware platforms throughout the production lifecycle.
Compensation
The target salary range for this position is 147,900 - 180,000 USD The salary offered will be determined by the candidate's location, qualifications, experience, and education and may be outside of this range.
Responsibilities
Evaluate and specify design and validation requirements
Drive execution across multiple internal and external engineering teams
Debug complex system issues
Lead mid-level hardware development projects from start to finish
Collaborate with development engineers, commodity teams, QA teams, manufacturing teams, field support, and external development partners
Requirements
Bachelor’s degree in Electrical Engineering, Computer Engineering, or a related technical field
As a Senior Hardware Engineer – FPGA & Platform Security on SPARC, you will help define and build the hardware root of trust that protects Azure’s fleet, from silicon and FPGA prototypes through firmware, BMC, and datacenter deployment.
Locations (2)
Redmond, Washington, United States
Mountain View, California, United States
Compensation
Hardware Engineering IC4 - The typical base pay range for this role across the U.S. is USD $119,800 - $234,700 per year. There is a different range applicable to specific work locations, within the San Francisco Bay area and New York City metropolitan area, and the base pay range for this role in those locations is USD $160,200 - $261,000 per year.
Responsibilities
Define requirements, specifications, and interface definitions for server platform features, including trust and integrity capabilities such as secure boot, attestation, and firmware recovery.
Lead bring-up of new server, SoC, and FPGA-based platforms, from first power-on through firmware, BMC, and OS boot, and work with hardware and firmware partners to resolve issues quickly.
Set up, maintain, and evolve lab infrastructure, including racks, networking, power, debug tooling, and remote management access, so engineers can validate new platforms efficiently.
FPGA Design Engineer responsible for efficient implementation of signal processing algorithms for Silvus' MIMO wireless networking products, supporting R&D and field deployment.
Compensation
$110,000 - $150,000 / annually
Responsibilities
Digital design architecting for wireless communication projects
Fixed point design of signal processing blocks with systems engineers
RTL coding, simulation, and test bench development
FPGA synthesis and timing closure
Hardware verification and troubleshooting with logic analyzers
Requirements
Bachelor of Science in Electrical Engineering, Computer Science, or related field
Advanced degree (M.S. or Ph.D.) in Electrical Engineering, Computer Science, or related field
Nice to have: Master of Science in Electrical Engineering
Nice to have: MATLAB
Nice to have: communication systems on FPGA or ASIC designs
Lead design and development of custom silicon IP for Microsoft’s Azure Cobalt chips, collaborating across architecture, firmware, verification, and physical design teams to deliver high‑performance, power‑efficient RTL and FPGA solutions.
Locations (2)
Redmond, Washington, United States
United States
Compensation
Silicon Engineering IC5 - The typical base pay range for this role across the U.S. is USD $142,800 - $274,800 per year. There is a different range applicable to specific work locations, within the San Francisco Bay area and New York City metropolitan area, and the base pay range for this role in those locations is USD $188,000 - $304,200 per year.
Responsibilities
Own and lead FPGA design environment efforts for rapid IP prototyping and design validation including root‑cause analysis of complex system issues.
Own development of custom IP RTL from microarchitecture through RTL implementation, verification, and post‑silicon validation.
Collaborate with architecture, SoC, firmware, verification, and physical design teams to deliver high‑quality FPGA and IP solutions.
Develop high‑performance, power‑efficient RTL designs and drive PPA optimization across the design lifecycle.
Senior FPGA / RTL Design Engineer - Signal Processing
Lead electronics development for space and terrestrial robotics, designing analog, digital, and power circuits, prototyping, testing, and integrating into missions.
Compensation
$115,544 - $138,008
Responsibilities
Own technical development of electronics, including specification, architecture, simulation, PCB design, laboratory testing, and mission infusion
Design analog, digital, and power electronics circuits for space and terrestrial robotics
Identify candidate technologies, design test fixtures, and support heavy ion testing to evaluate new parts for radiation effects
Collaborate with JPLers across disciplines to integrate your designs into complex robotic missions and instrument systems
Dream up and propose new projects to solve the hardest problems in space and on earth
Requirements
Bachelor’s degree in electrical engineering, robotics engineering, or similar technical discipline
Master’s degree in a similar discipline
Ph.D. in a similar discipline
Nice to have: lead new hardware projects
Nice to have: propose new electronics projects and win funding
We are seeking a talented FPGA Design Engineer with industry experience in wireless digital communications, networking, and/or cryptography to join our team developing advanced wireless digital communication and electronic warfare systems.
Responsibilities
Participate in the full FPGA development lifecycle, including bids and proposals, requirements definition, specification development and maintenance, RTL design and coding, simulation, synthesis, place and route, verification through simulation and unit testing, system integration, and ongoing support.
Participate in code and design reviews
Ensure that high-speed digital FPGA designs meet written specifications within a DoW process-controlled work environment
Prototype and integrate root-of-trust and HSM capabilities (for example, Caliptra) on FPGA and emulation platforms, and develop validation plans that cover normal, fault, and recovery scenarios.
Build diagnostics, telemetry, and automated recovery tools that help fleet hardware detect problems, report its health, and return to a known-good state with minimal manual intervention.
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