Own hardware safety analysis for processor IP configurations and perform SoC-level safety analysis for Custom Silicon programs, contributing to safety architecture for ARC MIPS processor IP certified to ISO 26262.
Compensation
The exact Salary will be determined based on qualifications, experience and location.
Responsibilities
Own hardware safety analysis for processor IP configurations: FMEDA, DFMEA, DFA and FTA, through to external assessment
Perform SoC-level safety analysis for Custom Silicon programs: integration of safety elements, system-level FMEDA, and the safety concept at the SoC boundary
Analyze dependent failures and freedom from interference across IP boundaries within an SoC
Derive and track safety metrics (SPFM, LFM, PMHF) and drive diagnostic coverage improvement together with the STL and verification teams
Define and review safety mechanisms at RTL level — ECC, parity, lockstep, register protection, watchdog — and verify they meet the claimed diagnostic coverage
Requirements
Master's or Bachelor's degree in Electrical/Electronic Engineering, Computer Engineering or a related field
Nice to have: ISO 26262 certification or formal training
Nice to have: Safety Element out of Context (SEooC) supplier experience
Nice to have: Fault simulation tooling (VC Z01X or equivalent)
Nice to have: Scripting and automation (Python, TCL)
Build and own the FPGA-based platforms that emulate mixed-signal power ASICs before silicon, validating real-time digital, mixed-signal, and power-control architectures pre-silicon.
Responsibilities
Partner closely with silicon RTL and DSP architects to bring ASIC designs up on FPGA
Adapt ASIC RTL for FPGA emulation while preserving functional equivalence to the golden design
Map designs onto the FPGA fabric to fit and to hit emulation speed
Build the real-time environment around the digital core: model or interface to the analog and power stages
Develop AI-based tools for the CAD Team at Apple, integrating models with engineering systems, assessing tool quality, automating tasks, and documenting progress.
Responsibilities
Develop AI-based tools that help engineers find information and solve problems more quickly.
Connect AI models to the engineering systems and data the team uses day to day.
Assess the quality and reliability of these tools, and look for ways to improve them.
Automate repetitive engineering and support tasks.
Document your work and present your progress to the team.
Requirements
Studying towards a BSc or MSc in Electrical/Electronic Engineering, Computer Science, Computer Engineering or a related subject.
As an ASIC STA Engineer, you will have responsibilities spanning all aspects of SoC design in terms of timing. Key responsibilities include timing sign-off, STA and sign-off flow development, ownership of Full chip, IP, and block level timing constraints both for regular and custom timing requirements from synthesis to sign-off to achieve sign-off quality timing constraints.
Locations (2)
Haifa, Haifa District, Israel
Herzliya, Tel Aviv District, Israel
Responsibilities
timing sign-off
STA and sign-off flow development
ownership of Full chip, IP, and block level timing constraints
interact with RTL designer to understand design intent and clock structure
Take part in the large scale SoC physical design cycle from netlist to tape-out, including full flow of back-end implementation and verification always meeting schedule and design goals.
Responsibilities
Own block level PnR, floor-planning, clock and power distribution
Get involved with static timing closure with commercial tools
Do power & noise analysis (EM/IR-Drop/Xtalk) as well as layout verification (DRC/LVS)
Develop and validate dedication low power clock network guidelines
Resolve design and flow issues related to physical design and identify potential solutions
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