Internship in various hardware engineering disciplines at Western Digital.
Locations (6)
Colorado Springs, Colorado, United States
Irvine, California, United States
Longmont, Colorado, United States
Fremont, California, United States
Rochester, Minnesota, United States
San Jose, California, United States
Compensation
The salary range is what we believe to be the range of possible compensation for this role at the time of this posting. We may ultimately pay more or less than the posted range and this range is only applicable for jobs to be performed in California, Colorado, New York or remote jobs that can be performed in California, Colorado and New York.
Responsibilities
Design and verify ASIC architectures and digital logic
Build simulations and validate complex hardware designs
Support the ASIC development lifecycle
Optimize performance, power, and reliability
Collaborate across hardware, firmware, and systems engineering teams
Detail-oriented Electrical Engineer to support design and implementation of complex wearable electro-optical systems from concept to production.
Responsibilities
Design, test, debug, and verify complex hardware using analog, digital, and power electronics circuits.
Take ownership of electronic subsystems from component selection, circuit design, and prototype evaluation through system-level integration and design verification.
Investigate and implement component replacements for obsolete components.
Perform, as well as lead technicians on, verification testing, debugging, and root cause analysis.
Provide schedule and budget input to support project.
The starting salary range posted for this position is $147,400.00 to $198,200.00 and reflects the projected salary range for new hires in this position in U.S. and/or Canada locations, not including incentive compensation*, equity, or benefits.
Lead the design and development of custom circuits for high-speed and low-power SRAM and low-power configuration RAM (CRAM) and manage the full embedded memory design flow.
Compensation
Base Pay Range
250,000.00
In addition to base pay, this role may be eligible for variable/ incentive compensation and/ or equity.
Responsibilities
Design and develop custom memory circuits
Develop memory architectures in advanced semiconductor technologies
Perform schematic capture, simulation, and margin verification
Oversee layout planning and pitch-matched designs
Collaborate with architecture and design teams on PPA and yield targets
This is a hands-on, fast-paced engineering role for an expert problem solver tasked with rapidly responding to and resolving systemic electrical issues in a portfolio of handheld, tablet and wearable products.
Responsibilities
Design, test, and validate cost-effective hardware solutions, including component changes, PCB layout modifications, and firmware adjustments
Develop and document product enhancements and cost-reduction modifications for the existing product portfolio
Manage the implementation of rolling changes into production in coordination with manufacturing and supply chain teams
Lead technical investigations into systemic electrical hardware issues escalated from technical support and directly from customers
Perform hands-on failure analysis, component-level troubleshooting, and replication of field failures in a lab environment
Senior Circuit Designer within our Digital Design Engineering group, responsible for developing innovative ASICs and leading SRAM compiler IP requirements.
Responsibilities
Drive the development of SRAM, register files, and latch arrays to enable high-performance, low-power design.
Lead the SRAM compiler IP requirements for foundry, vendors, and internal IP teams.
Understand the complete design flow spectrum, including DFT and testing aspects of compiler IPs, and integrate them into our SOCs.
Collaborate with logic/architecture teams to capture specifications of SRAM, register files, and latch arrays, driving their implementation.
Requirements
Bachelor’s in Electrical Engineering (BSEE)
Nice to have: Masters/PhD in Electrical Engineering
Nice to have: tape-out of high-performance, low-power circuit design
Nice to have: ML-based programming algorithms
Nice to have: automation solutions for rapid and dynamic design
The salary range is what we believe to be the range of possible compensation for this role at the time of this posting. We may ultimately pay more or less than the posted range and this range is only applicable for jobs to be performed in California, Colorado, New York or remote jobs that can be performed in California, Colorado and New York.
Responsibilities
Design and verify ASIC architectures and digital logic
Build simulations and validate complex hardware designs
Support the ASIC development lifecycle
Optimize performance, power, and reliability
Collaborate across hardware, firmware, and systems engineering teams
Requirements
Bachelor’s, Master’s, or Ph.D. degree in Computer Science, Computer Engineering, Electrical Engineering, Mechanical Engineering, Systems Engineering, Software Engineering, Manufacturing Engineering, Industrial Engineering, Mechatronics, Materials Engineering, Data Science, or a related engineering or technical discipline
Fullchip Floorplan by understanding the architecture of the design, foundry integration guidelines and IP placement constraints
Collaborate with the system and package design teams to understand the requirements and incorporate into the fullchip floorplan
Perform hierarchical implementation flow, including partition, pin assignment, clock plan and bump planning; Hands-on experience with Fullchip clock mesh and Flex-HTree methods
RTL-to-GDSII implementation: Floorplan, Power Grid plan, place and route, static timing analysis, power integrity, physical verification and equivalence checks with a focus on performance, power and die size optimization.
Analyze existing tool flows and methodologies, identifying efficiency gaps and implementing incremental or transformative enhancements.
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