Internship in CPU IP design and verification for RISC-V processor development
Locations (2)
Austin, Texas, United States
Santa Clara, California, United States
Compensation
$20.00 - $40.00
Responsibilities
Support RISC-V CPU microarchitecture and SystemVerilog RTL design and development
Contribute to CPU functions including instruction fetch and decode, execution, load/store, caches and memory interfaces, control and status registers, exceptions, and interrupts
Develop verification tests, assertions, checkers, and functional coverage for CPU features
Run CPU simulations and regressions and debug failures using logs, architectural traces, and waveforms
Verify processor functionality across instructions, privilege modes, memory operations, and architectural corner cases
Internship in CPU IP Design & Verification for RISC-V processor development at GlobalFoundries.
Locations (2)
Austin, Texas, United States
Santa Clara, California, United States
Compensation
$20.00 - $40.00
Responsibilities
Support RISC-V CPU microarchitecture and SystemVerilog RTL design and development
Contribute to CPU functions including instruction fetch and decode, execution, load/store, caches and memory interfaces, control and status registers, exceptions, and interrupts
Develop verification tests, assertions, checkers, and functional coverage for CPU features
Run CPU simulations and regressions and debug failures using logs, architectural traces, and waveforms
Verify processor functionality across instructions, privilege modes, memory operations, and architectural corner cases
Requirements
T
Member of Technical Staff
True Talent Solutions Partners · Posted Nov 10, 2026
Architect and drive the AI Software Stack by establishing best practices and optimizing performance from the lowest-level GPU kernels to large-scale distributed systems.
Responsibilities
Architect and drive the AI Software Stack
Optimize performance from lowest-level GPU kernels to large-scale distributed systems
Leverage Large Language Models (LLMs) and agent-based technologies to accelerate the AMD ROCm ecosystem
Accelerate applications such as foundation models and autonomous AI agents
Contribute to the entire co-design lifecycle, influencing future GPU architectures
Lead system performance engineering for Qualcomm Snapdragon chipsets, focusing on power, performance, and thermal behavior.
Compensation
$155,400.00 - $233,200.00
Responsibilities
Identify sustained and transient thermal and electrical requirements and lead investigations around limits management hardware architectures and protection mechanisms
Define and develop next generation thermal and limits management strategies for Qualcomm products, with a priority on server business unit needs
Define and conduct thermal and limit systems testing and validation on silicon and system-level platforms
Work closely with power and performance teams to optimize thermal and power trade-offs
Define and document thermal, performance and power analysis plans and updates for system use-cases across multiple workloads (CPU, GPU, AI/ML) as well as concurrent scenarios
Research, design, develop, simulate, and/or validate systems-level software, hardware, architecture, algorithms, and solutions that enable the development of cutting-edge technology, optimizing performance for Snapdragon Chipsets.
Compensation
Pay range and Other Compensation & Benefits: $129,500.00 - $194,300.00
Responsibilities
Enable, profile and analyze complex concurrent system use-cases in both emulation and software environments (Android/Linux/Windows)
Define and document performance and power analysis plans for system use-cases across multiple workloads (CPU, GPU, AI/ML) as well as concurrent scenarios
Identify areas of performance optimization in the SoC for both Software and Hardware architectures
Direct triage of complex performance issues to determine root-cause and present results to internal and external stakeholders
Collaborate with cross-functional teams (product management, hardware, and software engineering, etc.) to implement optimal power, performance, and thermal solutions
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products.
Responsibilities
Develop architecture specifications that meet current and future computing requirements for AI/ML roadmap.
Develop architectural and microarchitectural power/performance models, microarchitecture and evaluate quantitative and qualitative performance and power analysis.
Partner with hardware design, software, compiler, Machine Learning (ML) model and research teams for effective hardware/software co-design, creating high performance hardware/software interfaces.
Evaluate different silicon solutions for executing Google’s data center Artificial Intelligence (AI) accelerator roadmap, components, vendor co-developments, custom designs and chiplets.
Create high performance hardware/software interfaces.
Requirements
Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field
Nice to have: Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science
Nice to have: experience working with software teams optimizing the hardware/software interface
Nice to have: experience in estimating performance by analysis, modeling, and network simulation
Nice to have: experience in programming languages (e.g., C++, Python)
Define and drive the AI performance benchmarking and workload characterization strategy across CPU, GPU, APU, NPU, and heterogeneous platforms.
Benchmark AI inference workloads using PyTorch, ONNX Runtime, vLLM, llama.cpp, TensorFlow, and related frameworks and runtimes.
Analyze key performance metrics, including latency, throughput, time to first token, tokens per second, memory utilization, power consumption, and performance per watt.
Profile workloads and identify bottlenecks across AI frameworks, runtimes, libraries, drivers, operating systems, firmware, memory subsystems, and hardware.
Lead complex root-cause analysis and recommend optimizations related to quantization, graph execution, kernels, memory usage, workload scheduling, and heterogeneous compute utilization.
Requirements
Bachelor’s or master’s degree in Computer Engineering, Electrical Engineering, Computer Science, Artificial Intelligence, Machine Learning, or a related technical field
This engineer will improve end-to-end large language model (LLM) inference performance on Positron's custom AI accelerators, including our FPGA-based Atlas systems and our Titan systems built on the Asimov ASIC.
Compensation
The base salary range for this role is $200,000 – $300,000.
Responsibilities
Profile and optimize latency, throughput, utilization, and efficiency across hardware-accelerated attention, accelerator configuration, the device runtime, host software, and on-device execution.
Use performance counters, hardware and software traces, telemetry, and simulation to isolate regressions and validate fixes.
Develop and optimize distributed inference capabilities, including efficient KV cache management and data movement across heterogeneous hardware.
Build representative benchmarks and workload traces that expose bottlenecks in compute, memory, chip-to-chip interconnect, networking, scheduling, and model loading.
Partner with test engineers embedded in the team to turn performance findings into durable regression tests and release gates.
AI Solution Architecture DirectorSK hynix America · San Jose, US
MTS Software Development EngineerAdvanced Micro Devices, Inc · Santa Clara, US
Staff Thermal Limits EngineerQualcomm · San Diego, US
AI/ML Hardware Architect, Cloud, SiliconGoogle · Bengaluru, India
Performance & Debug Software Engineer – AI InferencePositron Corporation · Remote, US